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Commit a8e3ced4 authored by Kelvin Cheung's avatar Kelvin Cheung Committed by Stephen Boyd
Browse files

clk: Loongson1: Refactor Loongson1 clock 



Factor out the common functions into loongson1/clk.c
to support both Loongson1B and Loongson1C. And, put
the rest into loongson1/clk-loongson1b.c.

Signed-off-by: default avatarKelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 5963f19c

drivers/clk/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,6 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o 
obj-$(CONFIG_COMMON_CLK_CS2000_CP)	+= clk-cs2000-cp.o

obj-$(CONFIG_ARCH_EFM32)		+= clk-efm32gg.o

obj-$(CONFIG_ARCH_HIGHBANK)		+= clk-highbank.o

obj-$(CONFIG_MACH_LOONGSON32)		+= clk-ls1x.o

obj-$(CONFIG_COMMON_CLK_MAX77686)	+= clk-max77686.o

obj-$(CONFIG_ARCH_MB86S7X)		+= clk-mb86s7x.o

obj-$(CONFIG_ARCH_MOXART)		+= clk-moxart.o
@@ -61,6 +60,7 @@ obj-$(CONFIG_ARCH_HISI) += hisilicon/ 
obj-$(CONFIG_ARCH_MXC)			+= imx/

obj-$(CONFIG_MACH_INGENIC)		+= ingenic/

obj-$(CONFIG_COMMON_CLK_KEYSTONE)	+= keystone/

obj-$(CONFIG_MACH_LOONGSON32)		+= loongson1/

obj-$(CONFIG_ARCH_MEDIATEK)		+= mediatek/

obj-$(CONFIG_COMMON_CLK_AMLOGIC)	+= meson/

obj-$(CONFIG_MACH_PIC32)		+= microchip/

drivers/clk/loongson1/Makefile

0 → 100644
+2 −0
Original line number Diff line number Diff line 
obj-y				+= clk.o

obj-$(CONFIG_LOONGSON1_LS1B)	+= clk-loongson1b.o

drivers/clk/clk-ls1x.c→drivers/clk/loongson1/clk-loongson1b.c

+4 −47
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2012 Zhang, Keguang <keguang.zhang@gmail.com>

 * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com>

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the
@@ -10,25 +10,16 @@ 
#include <linux/clkdev.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include <linux/slab.h>

#include <linux/err.h>



#include <loongson1.h>

#include "clk.h"



#define OSC		(33 * 1000000)

#define DIV_APB		2



static DEFINE_SPINLOCK(_lock);



static int ls1x_pll_clk_enable(struct clk_hw *hw)

{

	return 0;

}



static void ls1x_pll_clk_disable(struct clk_hw *hw)

{

}



static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,

					  unsigned long parent_rate)

{
@@ -43,44 +34,9 @@ static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw, 
}



static const struct clk_ops ls1x_pll_clk_ops = {

	.enable = ls1x_pll_clk_enable,

	.disable = ls1x_pll_clk_disable,

	.recalc_rate = ls1x_pll_recalc_rate,

};



static struct clk_hw *__init clk_hw_register_pll(struct device *dev,

						 const char *name,

						 const char *parent_name,

						 unsigned long flags)

{

	int ret;

	struct clk_hw *hw;

	struct clk_init_data init;



	/* allocate the divider */

	hw = kzalloc(sizeof(struct clk_hw), GFP_KERNEL);

	if (!hw) {

		pr_err("%s: could not allocate clk_hw\n", __func__);

		return ERR_PTR(-ENOMEM);

	}



	init.name = name;

	init.ops = &ls1x_pll_clk_ops;

	init.flags = flags | CLK_IS_BASIC;

	init.parent_names = (parent_name ? &parent_name : NULL);

	init.num_parents = (parent_name ? 1 : 0);

	hw->init = &init;



	/* register the clock */

	ret = clk_hw_register(dev, hw);

	if (ret) {

		kfree(hw);

		hw = ERR_PTR(ret);

	}



	return hw;

}



static const char * const cpu_parents[] = { "cpu_clk_div", "osc_33m_clk", };

static const char * const ahb_parents[] = { "ahb_clk_div", "osc_33m_clk", };

static const char * const dc_parents[] = { "dc_clk_div", "osc_33m_clk", };
@@ -93,7 +49,8 @@ void __init ls1x_clk_init(void) 
	clk_hw_register_clkdev(hw, "osc_33m_clk", NULL);



	/* clock derived from 33 MHz OSC clk */

	hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk", 0);

	hw = clk_hw_register_pll(NULL, "pll_clk", "osc_33m_clk",

				 &ls1x_pll_clk_ops, 0);

	clk_hw_register_clkdev(hw, "pll_clk", NULL);



	/* clock derived from PLL clk */

drivers/clk/loongson1/clk.c

0 → 100644
+43 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com>

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */



#include <linux/clk-provider.h>

#include <linux/slab.h>



struct clk_hw *__init clk_hw_register_pll(struct device *dev,

					  const char *name,

					  const char *parent_name,

					  const struct clk_ops *ops,

					  unsigned long flags)

{

	int ret;

	struct clk_hw *hw;

	struct clk_init_data init;



	/* allocate the divider */

	hw = kzalloc(sizeof(*hw), GFP_KERNEL);

	if (!hw)

		return ERR_PTR(-ENOMEM);



	init.name = name;

	init.ops = ops;

	init.flags = flags | CLK_IS_BASIC;

	init.parent_names = (parent_name ? &parent_name : NULL);

	init.num_parents = (parent_name ? 1 : 0);

	hw->init = &init;



	/* register the clock */

	ret = clk_hw_register(dev, hw);

	if (ret) {

		kfree(hw);

		hw = ERR_PTR(ret);

	}



	return hw;

}

drivers/clk/loongson1/clk.h

0 → 100644
+19 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2012-2016 Zhang, Keguang <keguang.zhang@gmail.com>

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */



#ifndef __LOONGSON1_CLK_H

#define __LOONGSON1_CLK_H



struct clk_hw *clk_hw_register_pll(struct device *dev,

				   const char *name,

				   const char *parent_name,

				   const struct clk_ops *ops,

				   unsigned long flags);



#endif /* __LOONGSON1_CLK_H */