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Commit c6ab4979 authored by Prasad Sodagudi's avatar Prasad Sodagudi Committed by Runmin Wang
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clocksource: arch_timer: Use _no_log variants while accessing registers 



arch_timer register accesses happen more frequently flooding the
RTB logs. Since they are not that useful for debugging purposes,
use _no_log variants while accessing those registers.

Change-Id: Ide35ef1a01e4792c1b3b7b7be7ad3f069dc2f694
Signed-off-by: default avatarPrasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: default avatarSatya Durga Srinivasu Prabhala <satyap@codeaurora.org>
Signed-off-by: default avatarKyle Yan <kyan@codeaurora.org>
Signed-off-by: default avatarRunmin Wang <runminw@codeaurora.org>
parent 2ce60629

drivers/clocksource/arm_arch_timer.c

+12 −12
Original line number Diff line number Diff line
@@ -98,20 +98,20 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, 
		struct arch_timer *timer = to_arch_timer(clk);

		switch (reg) {

		case ARCH_TIMER_REG_CTRL:

			writel_relaxed(val, timer->base + CNTP_CTL);

			writel_relaxed_no_log(val, timer->base + CNTP_CTL);

			break;

		case ARCH_TIMER_REG_TVAL:

			writel_relaxed(val, timer->base + CNTP_TVAL);

			writel_relaxed_no_log(val, timer->base + CNTP_TVAL);

			break;

		}

	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {

		struct arch_timer *timer = to_arch_timer(clk);

		switch (reg) {

		case ARCH_TIMER_REG_CTRL:

			writel_relaxed(val, timer->base + CNTV_CTL);

			writel_relaxed_no_log(val, timer->base + CNTV_CTL);

			break;

		case ARCH_TIMER_REG_TVAL:

			writel_relaxed(val, timer->base + CNTV_TVAL);

			writel_relaxed_no_log(val, timer->base + CNTV_TVAL);

			break;

		}

	} else {
@@ -129,20 +129,20 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, 
		struct arch_timer *timer = to_arch_timer(clk);

		switch (reg) {

		case ARCH_TIMER_REG_CTRL:

			val = readl_relaxed(timer->base + CNTP_CTL);

			val = readl_relaxed_no_log(timer->base + CNTP_CTL);

			break;

		case ARCH_TIMER_REG_TVAL:

			val = readl_relaxed(timer->base + CNTP_TVAL);

			val = readl_relaxed_no_log(timer->base + CNTP_TVAL);

			break;

		}

	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {

		struct arch_timer *timer = to_arch_timer(clk);

		switch (reg) {

		case ARCH_TIMER_REG_CTRL:

			val = readl_relaxed(timer->base + CNTV_CTL);

			val = readl_relaxed_no_log(timer->base + CNTV_CTL);

			break;

		case ARCH_TIMER_REG_TVAL:

			val = readl_relaxed(timer->base + CNTV_TVAL);

			val = readl_relaxed_no_log(timer->base + CNTV_TVAL);

			break;

		}

	} else {
@@ -869,9 +869,9 @@ static u64 arch_counter_get_cntvct_mem(void) 
	u32 vct_lo, vct_hi, tmp_hi;



	do {

		vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);

		vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);

		tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);

		vct_hi = readl_relaxed_no_log(arch_counter_base + CNTVCT_HI);

		vct_lo = readl_relaxed_no_log(arch_counter_base + CNTVCT_LO);

		tmp_hi = readl_relaxed_no_log(arch_counter_base + CNTVCT_HI);

	} while (vct_hi != tmp_hi);



	return ((u64) vct_hi << 32) | vct_lo;
@@ -1241,7 +1241,7 @@ arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem) 
		return NULL;

	}



	cnttidr = readl_relaxed(cntctlbase + CNTTIDR);

	cnttidr = readl_relaxed_no_log(cntctlbase + CNTTIDR);



	/*

	 * Try to find a virtual capable frame. Otherwise fall back to a