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Commit 2ce60629 authored by Channagoud Kadabi's avatar Channagoud Kadabi Committed by Runmin Wang
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irqchip: GICv3: Check if GIC register access is controlled



Add support to configure ITS registers only if higher
exception levels have not already configured them.

Change-Id: I45eaa51e56e034d011cf41d8b924fb674f63447d
Signed-off-by: default avatarHanumant Singh <hanumant@codeaurora.org>
Signed-off-by: default avatarPuja Gupta <pujag@codeaurora.org>
Signed-off-by: default avatarAbhimanyu Kapur <abhimany@codeaurora.org>
[ckadabi: resolved merge conflict]
Signed-off-by: default avatarChannagoud Kadabi <ckadabi@codeaurora.org>
[runminw: resolved merge conflict]
Signed-off-by: default avatarRunmin Wang <runminw@codeaurora.org>
parent 923054ff
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+9 −0
Original line number Diff line number Diff line
@@ -41,6 +41,15 @@ config ARM_GIC_V3_ITS
	depends on PCI
	depends on PCI_MSI

config ARM_GIC_V3_ACL
	bool "GICv3 Access control"
	depends on ARM_GIC_V3
	help
	  Access to GIC ITS address space is controlled by EL2.
	  Kernel has no permission to access GIC ITS address space.
	  If you wish to enforce the Acces control then set this
	  option to Y, if you are unsure please say N.

config ARM_NVIC
	bool
	select IRQ_DOMAIN
+4 −2
Original line number Diff line number Diff line
@@ -538,7 +538,8 @@ static void gic_cpu_init(void)
	gic_cpu_config(rbase, gic_redist_wait_for_rwp);

	/* Give LPIs a spin */
	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
					!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))
		its_cpu_init();

	/* initialise system registers */
@@ -952,7 +953,8 @@ static int __init gic_init_bases(void __iomem *dist_base,

	set_handle_irq(gic_handle_irq);

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())
	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&
			!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))
		its_init(handle, &gic_data.rdists, gic_data.domain);

	gic_smp_init();