Commit 923054ff authored Sep 20, 2016 by Channagoud Kadabi Committed by Runmin Wang Jul 21, 2017

drivers: GICv3: Add mb() after the read of GIC registers



As per the GICv3 architecture spec section "Observability
of GIC Register Accesses", architecture execution of the "DSB"
gurantees the read/write access to ICC_PMR_EL1 and ICC_SGI1R_EL1
are observed by the associated restributor.

Change-Id: I9c7bcdee51f71d369e2a6f04faf7a22c3c1381bc
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
[abhimany: relocate mb()'s to header files]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
[ckadabi: remove sync of some of register that is already upstream]
Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: Runmin Wang <runminw@codeaurora.org>

parent 5bd6c7c6

arch/arm64/include/asm/arch_gicv3.h

+4 −0

Original line number	Diff line number	Diff line
		@@ -79,6 +79,8 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
		static inline void gic_write_pmr(u32 val)
		{
		write_sysreg_s(val, SYS_ICC_PMR_EL1);
		/* As per the architecture specification */
		mb();
		}

		static inline void gic_write_ctlr(u32 val)
		@@ -96,6 +98,8 @@ static inline void gic_write_grpen1(u32 val)
		static inline void gic_write_sgi1r(u64 val)
		{
		write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
		/* As per the architecture specification */
		mb();
		}

		static inline u32 gic_read_sre(void)