clk: qcom: npucc-sm8150: Minor change to the CRC enable sequence

As part of the CRC enable sequence for the npu_cc_cal_dp_clk_src
RCG, the clock driver currently sets the RCGs rate to the VDD_MIN
frequency. However, that's not a corner that's supported on all
versions of the target. Set the RCG to the lowest supported
frequency instead.

Change-Id: I2c318a2b5870fc7ab2ea1481235725fc4eb9a7d0
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>