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Commit bc887246 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: STMMAC changes for SA8155 LV"

parents 8a1a1d4a 1f070ef4

Documentation/devicetree/bindings/net/qcom,stmmac-ethqos.txt

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+179 −0
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* STMicroelectronics 10/100/1000 Ethernet driver (GMAC)



Required properties:

- compatible: Should be "qcom,stmmac-ethqos",

	For backwards compatibility: "st,spear600-gmac" is also supported.

- reg: Address and length of the register set for the device

- interrupt-parent: Should be the phandle for the interrupt controller

  that services interrupts for this device

- interrupts: Should contain the STMMAC interrupts

- interrupt-names: Should contain a list of interrupt names corresponding to

	the interrupts in the interrupts property, if available.

	Valid interrupt names are:

  - "macirq" (combined signal for various interrupt events)

  - "eth_wake_irq" (the interrupt to manage the remote wake-up packet detection)

  - "eth_lpi" (the interrupt that occurs when Tx or Rx enters/exits LPI state)

- phy-mode: See ethernet.txt file in the same directory.

- snps,reset-gpio 	gpio number for phy reset.

- snps,reset-active-low boolean flag to indicate if phy reset is active low.

- snps,reset-delays-us  is triplet of delays

	The 1st cell is reset pre-delay in micro seconds.

	The 2nd cell is reset pulse in micro seconds.

	The 3rd cell is reset post-delay in micro seconds.



Optional properties:

- resets: Should contain a phandle to the STMMAC reset signal, if any

- reset-names: Should contain the reset signal name "stmmaceth", if a

	reset phandle is given

- max-frame-size: See ethernet.txt file in the same directory

- clocks: If present, the first clock should be the GMAC main clock and

  the second clock should be peripheral's register interface clock. Further

  clocks may be specified in derived bindings.

- clock-names: One name for each entry in the clocks property, the

  first one should be "stmmaceth" and the second one should be "pclk".

- ptp_ref: this is the PTP reference clock; in case of the PTP is available

  this clock is used for programming the Timestamp Addend Register. If not

  passed then the system clock will be used and this is fine on some

  platforms.

- tx-fifo-depth: See ethernet.txt file in the same directory

- rx-fifo-depth: See ethernet.txt file in the same directory

- snps,pbl		Programmable Burst Length (tx and rx)

- snps,txpbl		Tx Programmable Burst Length. Only for GMAC and newer.

			If set, DMA tx will use this value rather than snps,pbl.

- snps,rxpbl		Rx Programmable Burst Length. Only for GMAC and newer.

			If set, DMA rx will use this value rather than snps,pbl.

- snps,no-pbl-x8	Don't multiply the pbl/txpbl/rxpbl values by 8.

			For core rev < 3.50, don't multiply the values by 4.

- snps,aal		Address-Aligned Beats

- snps,fixed-burst	Program the DMA to use the fixed burst mode

- snps,mixed-burst	Program the DMA to use the mixed burst mode

- snps,force_thresh_dma_mode	Force DMA to use the threshold mode for

				both tx and rx

- snps,force_sf_dma_mode	Force DMA to use the Store and Forward

				mode for both tx and rx. This flag is

				ignored if force_thresh_dma_mode is set.

- snps,en-tx-lpi-clockgating	Enable gating of the MAC TX clock during

				TX low-power mode

- snps,multicast-filter-bins:	Number of multicast filter hash bins

				supported by this device instance

- snps,perfect-filter-entries:	Number of perfect filter entries supported

				by this device instance

- snps,ps-speed: port selection speed that can be passed to the core when

		 PCS is supported. For example, this is used in case of SGMII

		 and MAC2MAC connection.

- snps,tso: this enables the TSO feature otherwise it will be managed by

		 MAC HW capability register. Only for GMAC4 and newer.

- AXI BUS Mode parameters: below the list of all the parameters to program the

			   AXI register inside the DMA module:

	- snps,lpi_en: enable Low Power Interface

	- snps,xit_frm: unlock on WoL

	- snps,wr_osr_lmt: max write outstanding req. limit

	- snps,rd_osr_lmt: max read outstanding req. limit

	- snps,kbbe: do not cross 1KiB boundary.

	- snps,blen: this is a vector of supported burst length.

	- snps,fb: fixed-burst

	- snps,mb: mixed-burst

	- snps,rb: rebuild INCRx Burst

- mdio: with compatible = "snps,dwmac-mdio", create and register mdio bus.

- Multiple RX Queues parameters: below the list of all the parameters to

				 configure the multiple RX queues:

	- snps,rx-queues-to-use: number of RX queues to be used in the driver

	- Choose one of these RX scheduling algorithms:

		- snps,rx-sched-sp: Strict priority

		- snps,rx-sched-wsp: Weighted Strict priority

	- For each RX queue

		- Choose one of these modes:

			- snps,dcb-algorithm: Queue to be enabled as DCB

			- snps,avb-algorithm: Queue to be enabled as AVB

		- snps,map-to-dma-channel: Channel to map

		- Specifiy specific packet routing:

			- snps,route-avcp: AV Untagged Control packets

			- snps,route-ptp: PTP Packets

			- snps,route-dcbcp: DCB Control Packets

			- snps,route-up: Untagged Packets

			- snps,route-multi-broad: Multicast & Broadcast Packets

		- snps,priority: RX queue priority (Range: 0x0 to 0xF)

- Multiple TX Queues parameters: below the list of all the parameters to

				 configure the multiple TX queues:

	- snps,tx-queues-to-use: number of TX queues to be used in the driver

	- Choose one of these TX scheduling algorithms:

		- snps,tx-sched-wrr: Weighted Round Robin

		- snps,tx-sched-wfq: Weighted Fair Queuing

		- snps,tx-sched-dwrr: Deficit Weighted Round Robin

		- snps,tx-sched-sp: Strict priority

	- For each TX queue

		- snps,weight: TX queue weight (if using a DCB weight algorithm)

		- Choose one of these modes:

			- snps,dcb-algorithm: TX queue will be working in DCB

			- snps,avb-algorithm: TX queue will be working in AVB

			  [Attention] Queue 0 is reserved for legacy traffic

			  and so no AVB is available in this queue.

		- Configure Credit Base Shaper (if AVB Mode selected):

			- snps,send_slope: enable Low Power Interface

			- snps,idle_slope: unlock on WoL

			- snps,high_credit: max write outstanding req. limit

			- snps,low_credit: max read outstanding req. limit

		- snps,priority: TX queue priority (Range: 0x0 to 0xF)

Examples:



	stmmac_axi_setup: stmmac-axi-config {

		snps,wr_osr_lmt = <0xf>;

		snps,rd_osr_lmt = <0xf>;

		snps,blen = <256 128 64 32 0 0 0>;

	};



	mtl_rx_setup: rx-queues-config {

		snps,rx-queues-to-use = <1>;

		snps,rx-sched-sp;

		queue0 {

			snps,dcb-algorithm;

			snps,map-to-dma-channel = <0x0>;

			snps,priority = <0x0>;

		};

	};



	mtl_tx_setup: tx-queues-config {

		snps,tx-queues-to-use = <2>;

		snps,tx-sched-wrr;

		queue0 {

			snps,weight = <0x10>;

			snps,dcb-algorithm;

			snps,priority = <0x0>;

		};



		queue1 {

			snps,avb-algorithm;

			snps,send_slope = <0x1000>;

			snps,idle_slope = <0x1000>;

			snps,high_credit = <0x3E800>;

			snps,low_credit = <0xFFC18000>;

			snps,priority = <0x1>;

		};

	};



	gmac0: ethernet@e0800000 {

		compatible = "st,spear600-gmac";

		reg = <0xe0800000 0x8000>;

		interrupt-parent = <&vic1>;

		interrupts = <24 23 22>;

		interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

		mac-address = [000000000000]; /* Filled in by U-Boot */

		max-frame-size = <3800>;

		phy-mode = "gmii";

		snps,multicast-filter-bins = <256>;

		snps,perfect-filter-entries = <128>;

		rx-fifo-depth = <16384>;

		tx-fifo-depth = <16384>;

		clocks = <&clock>;

		clock-names = "stmmaceth";

		snps,axi-config = <&stmmac_axi_setup>;

		mdio0 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,dwmac-mdio";

			phy1: ethernet-phy@0 {

			};

		};

		snps,mtl-rx-config = <&mtl_rx_setup>;

		snps,mtl-tx-config = <&mtl_tx_setup>;

	};

arch/arm64/boot/dts/qcom/sa8155-v2.dtsi

+5 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -19,6 +19,10 @@ 
	qcom,msm-id = <362 0x20000>;

};



&ethqos_hw {

	emac-core-version = <0x20010002>;

};



&emac_hw {

	emac-core-version = <4>;

	early-ethernet-en;

arch/arm64/boot/dts/qcom/sa8155.dtsi

+144 −0
Original line number Diff line number Diff line
@@ -632,6 +632,150 @@ 
		};

	};



	mtl_rx_setup: rx-queues-config {

		snps,rx-queues-to-use = <4>;

		snps,rx-sched-sp;



		queue0 {

			snps,dcb-algorithm;

			snps,map-to-dma-channel = <0x0>;

			snps,route-up;

			snps,priority = <0x1>;

		};



		queue1 {

			snps,dcb-algorithm;

			snps,map-to-dma-channel = <0x1>;

			snps,route-ptp;

		};



		queue2 {

			snps,avb-algorithm;

			snps,map-to-dma-channel = <0x2>;

			snps,route-avcp;

		};



		queue3 {

			snps,avb-algorithm;

			snps,map-to-dma-channel = <0x3>;

			snps,priority = <0xC>;

		};

	};



	mtl_tx_setup: tx-queues-config {

		snps,tx-queues-to-use = <5>;

		snps,tx-sched-sp;

		queue0 {

			snps,dcb-algorithm;

		};



		queue1 {

			snps,dcb-algorithm;

		};



		queue2 {

			snps,avb-algorithm;

			snps,send_slope = <0x1000>;

			snps,idle_slope = <0x1000>;

			snps,high_credit = <0x3E800>;

			snps,low_credit = <0xFFC18000>;

		};



		queue3 {

			snps,avb-algorithm;

			snps,send_slope = <0x1000>;

			snps,idle_slope = <0x1000>;

			snps,high_credit = <0x3E800>;

			snps,low_credit = <0xFFC18000>;

		};

	};



	ethqos_hw: qcom,ethernet@00020000 {

		compatible = "qcom,stmmac-ethqos";

		qcom,arm-smmu;

		reg = <0x20000 0x10000>,

			<0x36000 0x100>,

			<0x3D00000 0x300000>;

		reg-names = "stmmaceth", "rgmii","tlmm-central-base";

		clocks = <&clock_gcc GCC_EMAC_AXI_CLK>,

			<&clock_gcc GCC_EMAC_SLV_AHB_CLK>,

			<&clock_gcc GCC_EMAC_PTP_CLK>,

			<&clock_gcc GCC_EMAC_RGMII_CLK>;

		clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";

		snps,ptp-ref-clk-rate = <230400000>;

		snps,ptp-req-clk-rate = <57600000>;

		interrupts-extended = <&pdc 0 689 4>, <&pdc 0 699 4>,

			<&tlmm 124 2>;

		interrupt-names = "macirq", "eth_lpi",

			"phy-intr";

		qcom,msm-bus,name = "emac";

		qcom,msm-bus,num-cases = <4>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

			<98 512 0 0>, <1 781 0 0>, /* No vote */

			<98 512 2500 0>, <1 781 0 40000>, /* 10Mbps vote */

			<98 512 25000 0>, <1 781 0 40000>, /* 100Mbps vote */

			<98 512 250000 0>, <1 781 0 40000>; /* 1000Mbps vote */

		qcom,bus-vector-names = "0", "10", "100", "1000";

		snps,tso;

		rx-fifo-depth = <16384>;

		tx-fifo-depth = <32768>;

		snps,mtl-rx-config = <&mtl_rx_setup>;

		snps,mtl-tx-config = <&mtl_tx_setup>;

		snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_HIGH>;

		qcom,phy-intr-redirect = <&tlmm 124 GPIO_ACTIVE_LOW>;

		gdsc_emac-supply = <&emac_gdsc>;



		pinctrl-names = "dev-emac-mdc",

			"dev-emac-mdio",

			"dev-emac-rgmii_txd0_state",

			"dev-emac-rgmii_txd1_state",

			"dev-emac-rgmii_txd2_state",

			"dev-emac-rgmii_txd3_state",

			"dev-emac-rgmii_txc_state",

			"dev-emac-rgmii_tx_ctl_state",

			"dev-emac-rgmii_rxd0_state",

			"dev-emac-rgmii_rxd1_state",

			"dev-emac-rgmii_rxd2_state",

			"dev-emac-rgmii_rxd3_state",

			"dev-emac-rgmii_rxc_state",

			"dev-emac-rgmii_rx_ctl_state",

			"dev-emac-phy_intr",

			"dev-emac-phy_reset_state",

			"dev-emac_pin_pps_0";



		pinctrl-0 = <&emac_mdc>;

		pinctrl-1 = <&emac_mdio>;



		pinctrl-2 = <&emac_rgmii_txd0>;

		pinctrl-3 = <&emac_rgmii_txd1>;

		pinctrl-4 = <&emac_rgmii_txd2>;

		pinctrl-5 = <&emac_rgmii_txd3>;

		pinctrl-6 = <&emac_rgmii_txc>;

		pinctrl-7 = <&emac_rgmii_tx_ctl>;



		pinctrl-8 = <&emac_rgmii_rxd0>;

		pinctrl-9 = <&emac_rgmii_rxd1>;

		pinctrl-10 = <&emac_rgmii_rxd2>;

		pinctrl-11 = <&emac_rgmii_rxd3>;

		pinctrl-12 = <&emac_rgmii_rxc>;

		pinctrl-13 = <&emac_rgmii_rx_ctl>;



		pinctrl-14 = <&emac_phy_intr>;

		pinctrl-15 = <&emac_phy_reset_state>;

		pinctrl-16 = <&emac_pin_pps_0>;



		snps,reset-active-low;

		snps,reset-delays-us = <0 10000 100000>;

		phy-mode = "rgmii";



		ethqos_emb_smmu: ethqos_emb_smmu {

			compatible = "qcom,emac-smmu-embedded";

			iommus = <&apps_smmu 0x3C0 0x0>;

			qcom,iova-mapping = <0x80000000 0x40000000>;

		};

	};



	emac_hw: qcom,emac@00020000 {

		compatible = "qcom,emac-dwc-eqos";

		qcom,arm-smmu;

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

+54 −21
Original line number Diff line number Diff line
@@ -382,7 +382,8 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 
	int retry = 1000;



	/* Set CDR_EN */

	if (ethqos->emac_ver == EMAC_HW_v2_3_2)

	if (ethqos->emac_ver == EMAC_HW_v2_3_2 ||

	    ethqos->emac_ver == EMAC_HW_v2_1_2)

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,

			      0, SDCC_HC_REG_DLL_CONFIG);

	else
@@ -401,7 +402,8 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 
	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,

		      SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);



	if (ethqos->emac_ver != EMAC_HW_v2_3_2) {

	if (ethqos->emac_ver != EMAC_HW_v2_3_2 &&

	    ethqos->emac_ver != EMAC_HW_v2_1_2) {

		rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,

			      0, SDCC_HC_REG_DLL_CONFIG);
@@ -441,7 +443,8 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 
	rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,

		      SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);



	if (ethqos->emac_ver != EMAC_HW_v2_3_2) {

	if (ethqos->emac_ver != EMAC_HW_v2_3_2 &&

	    ethqos->emac_ver != EMAC_HW_v2_1_2) {

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,

			      0, SDCC_HC_REG_DLL_CONFIG2);
@@ -480,6 +483,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
			      RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,

			      RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);

		if (ethqos->emac_ver != EMAC_HW_v2_1_2)

			rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

				      0, RGMII_IO_MACRO_CONFIG2);

		rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
@@ -495,13 +499,17 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

			rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,

				      69, SDCC_HC_REG_DDR_CONFIG);

		else if (ethqos->emac_ver == EMAC_HW_v2_1_2)

			rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,

				      52, SDCC_HC_REG_DDR_CONFIG);

		else

			rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,

				      57, SDCC_HC_REG_DDR_CONFIG);

		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,

			      SDCC_DDR_CONFIG_PRG_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2 ||

		    ethqos->emac_ver == EMAC_HW_v2_1_2)

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

				      0, RGMII_IO_MACRO_CONFIG);

		else
@@ -520,6 +528,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
			      0, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,

			      0, RGMII_IO_MACRO_CONFIG);

		if (ethqos->emac_ver != EMAC_HW_v2_1_2)

			rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

				      0, RGMII_IO_MACRO_CONFIG2);

		rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
@@ -529,7 +538,8 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
			      BIT(6), RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      0, RGMII_IO_MACRO_CONFIG2);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2 ||

		    ethqos->emac_ver == EMAC_HW_v2_1_2)

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_IO_MACRO_CONFIG2);
@@ -545,7 +555,8 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2 ||

		    ethqos->emac_ver == EMAC_HW_v2_1_2)

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

				      0, RGMII_IO_MACRO_CONFIG);

		else
@@ -564,9 +575,11 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
			      0, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,

			      0, RGMII_IO_MACRO_CONFIG);

		if (ethqos->emac_ver != EMAC_HW_v2_1_2)

			rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

				      0, RGMII_IO_MACRO_CONFIG2);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2 ||

		    ethqos->emac_ver == EMAC_HW_v2_1_2)

			rgmii_updatel(ethqos,

				      RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,

				      RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
@@ -580,7 +593,8 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
			      RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      0, RGMII_IO_MACRO_CONFIG2);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2 ||

		    ethqos->emac_ver == EMAC_HW_v2_1_2)

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_IO_MACRO_CONFIG2);
@@ -596,7 +610,8 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2 ||

		    ethqos->emac_ver == EMAC_HW_v2_1_2)

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

				      0, RGMII_IO_MACRO_CONFIG);

		else
@@ -842,6 +857,7 @@ static void ethqos_pps_irq_config(struct qcom_ethqos *ethqos) 
static const struct of_device_id qcom_ethqos_match[] = {

	{ .compatible = "qcom,sdxprairie-ethqos", .data = &emac_v2_3_2_por},

	{ .compatible = "qcom,emac-smmu-embedded", },

	{ .compatible = "qcom,stmmac-ethqos", },

	{}

};
@@ -1168,8 +1184,10 @@ static int ethqos_update_rgmii_tx_drv_strength(struct qcom_ethqos *ethqos) 


	ETHQOSDBG("dwc_tlmm_central = %#lx\n", tlmm_central_base_addr);



	if (ethqos->emac_ver != EMAC_HW_v2_1_2) {

		reg_rgmii_io_pads_voltage =

		regulator_get_voltage(ethqos->reg_rgmii_io_pads);

	}



	ETHQOSINFO("IOMACRO pads voltage: %u uV\n", reg_rgmii_io_pads_voltage);
@@ -1418,8 +1436,23 @@ static int qcom_ethqos_probe(struct platform_device *pdev) 
		}

	}



	ethqos->emac_ver = rgmii_readl(ethqos,

				       EMAC_I0_EMAC_CORE_HW_VERSION_RGOFFADDR);

	if (of_property_read_bool(pdev->dev.of_node,

				  "emac-core-version")) {

		/* Read emac core version value from dtsi */

		ret = of_property_read_u32(pdev->dev.of_node,

					   "emac-core-version",

					   &ethqos->emac_ver);

		if (ret) {

			ETHQOSDBG(":resource emac-hw-ver! not in dtsi\n");

			ethqos->emac_ver = EMAC_HW_NONE;

			WARN_ON(1);

		}

	} else {

		ethqos->emac_ver =

		rgmii_readl(ethqos, EMAC_I0_EMAC_CORE_HW_VERSION_RGOFFADDR);

	}

	ETHQOSDBG(": emac_core_version = %d\n", ethqos->emac_ver);



	ethqos->ioaddr = (&stmmac_res)->addr;

	ethqos_update_rgmii_tx_drv_strength(ethqos);
@@ -1582,7 +1615,7 @@ static struct platform_driver qcom_ethqos_driver = { 
	.probe  = qcom_ethqos_probe,

	.remove = qcom_ethqos_remove,

	.driver = {

		.name           = "qcom-ethqos",

		.name           = DRV_NAME,

		.pm = &qcom_ethqos_pm_ops,

		.of_match_table = of_match_ptr(qcom_ethqos_match),

	},

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.h

+5 −0
Original line number Diff line number Diff line
@@ -131,8 +131,13 @@ do {\ 
#define EMAC_HW_NONE 0

#define EMAC_HW_v2_0_0 0x20000000

#define EMAC_HW_v2_1_0 0x20010000

#define EMAC_HW_v2_1_1 0x20010001

#define EMAC_HW_v2_1_2 0x20010002

#define EMAC_HW_v2_2_0 0x20020000

#define EMAC_HW_v2_3_0 0x20030000

#define EMAC_HW_v2_3_1 0x20030001

#define EMAC_HW_v2_3_2 0x20030002

#define EMAC_HW_vMAX 9



#define MII_BUSY 0x00000001

#define MII_WRITE 0x00000002