Loading drivers/clk/qcom/gcc-qcs405.c +2 −2 Original line number Diff line number Diff line Loading @@ -1044,12 +1044,12 @@ static struct clk_rcg2 hdmi_pclk_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_8, .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_pclk_clk_src", .parent_names = gcc_parent_names_8, .num_parents = 3, .ops = &clk_rcg2_ops, .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { Loading Loading
drivers/clk/qcom/gcc-qcs405.c +2 −2 Original line number Diff line number Diff line Loading @@ -1044,12 +1044,12 @@ static struct clk_rcg2 hdmi_pclk_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = gcc_parent_map_8, .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_pclk_clk_src", .parent_names = gcc_parent_names_8, .num_parents = 3, .ops = &clk_rcg2_ops, .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, .vdd_class = &vdd_cx, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { Loading