Merge back earlier cpuidle changes for v4.8. (b55a0262) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/x86/include/asm/topology.h

+1 −11

Original line number	Diff line number	Diff line
		@@ -25,16 +25,6 @@
		#ifndef _ASM_X86_TOPOLOGY_H
		#define _ASM_X86_TOPOLOGY_H

		#ifdef CONFIG_X86_32
		# ifdef CONFIG_SMP
		# define ENABLE_TOPO_DEFINES
		# endif
		#else
		# ifdef CONFIG_SMP
		# define ENABLE_TOPO_DEFINES
		# endif
		#endif

		/*
		* to preserve the visibility of NUMA_NO_NODE definition,
		* moved to there from here. May be used independent of
		@@ -123,7 +113,7 @@ extern const struct cpumask *cpu_coregroup_mask(int cpu);
		#define topology_physical_package_id(cpu) (cpu_data(cpu).phys_proc_id)
		#define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id)

		#ifdef ENABLE_TOPO_DEFINES
		#ifdef CONFIG_SMP
		#define topology_core_cpumask(cpu) (per_cpu(cpu_core_map, cpu))
		#define topology_sibling_cpumask(cpu) (per_cpu(cpu_sibling_map, cpu))

arch/x86/kernel/cpu/intel.c

+3 −4

Original line number	Diff line number	Diff line
		@@ -300,15 +300,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
		}

		/*
		* P4 Xeon errata 037 workaround.
		* P4 Xeon erratum 037 workaround.
		* Hardware prefetcher may cause stale data to be loaded into the cache.
		*/
		if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
		if (msr_set_bit(MSR_IA32_MISC_ENABLE,
		MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
		> 0) {
		MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
		pr_info("CPU: C0 stepping P4 Xeon detected.\n");
		pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
		pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
		}
		}

arch/x86/platform/atom/punit_atom_debug.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -23,6 +23,7 @@
		#include <linux/seq_file.h>
		#include <linux/io.h>
		#include <asm/cpu_device_id.h>
		#include <asm/intel-family.h>
		#include <asm/iosf_mbi.h>

		/* Power gate status reg */
		@@ -143,8 +144,8 @@ static void punit_dbgfs_unregister(void)
		(kernel_ulong_t)&drv_data }

		static const struct x86_cpu_id intel_punit_cpu_ids[] = {
		ICPU(55, punit_device_byt), /* Valleyview, Bay Trail */
		ICPU(76, punit_device_cht), /* Braswell, Cherry Trail */
		ICPU(INTEL_FAM6_ATOM_SILVERMONT1, punit_device_byt),
		ICPU(INTEL_FAM6_ATOM_AIRMONT, punit_device_cht),
		{}
		};

drivers/acpi/acpi_lpss.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -29,6 +29,7 @@ ACPI_MODULE_NAME("acpi_lpss");
		#ifdef CONFIG_X86_INTEL_LPSS

		#include <asm/cpu_device_id.h>
		#include <asm/intel-family.h>
		#include <asm/iosf_mbi.h>
		#include <asm/pmc_atom.h>

		@@ -229,8 +230,8 @@ static const struct lpss_device_desc bsw_spi_dev_desc = {
		#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }

		static const struct x86_cpu_id lpss_cpu_ids[] = {
		ICPU(0x37), /* Valleyview, Bay Trail */
		ICPU(0x4c), /* Braswell, Cherry Trail */
		ICPU(INTEL_FAM6_ATOM_SILVERMONT1), /* Valleyview, Bay Trail */
		ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */
		{}
		};

drivers/cpufreq/intel_pstate.c

+19 −18

Original line number	Diff line number	Diff line
		@@ -35,6 +35,7 @@
		#include <asm/msr.h>
		#include <asm/cpu_device_id.h>
		#include <asm/cpufeature.h>
		#include <asm/intel-family.h>

		#define ATOM_RATIOS 0x66a
		#define ATOM_VIDS 0x66b
		@@ -1334,29 +1335,29 @@ static void intel_pstate_update_util(struct update_util_data *data, u64 time,
		(unsigned long)&policy }

		static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
		ICPU(0x2a, core_params),
		ICPU(0x2d, core_params),
		ICPU(0x37, silvermont_params),
		ICPU(0x3a, core_params),
		ICPU(0x3c, core_params),
		ICPU(0x3d, core_params),
		ICPU(0x3e, core_params),
		ICPU(0x3f, core_params),
		ICPU(0x45, core_params),
		ICPU(0x46, core_params),
		ICPU(0x47, core_params),
		ICPU(0x4c, airmont_params),
		ICPU(0x4e, core_params),
		ICPU(0x4f, core_params),
		ICPU(0x5e, core_params),
		ICPU(0x56, core_params),
		ICPU(0x57, knl_params),
		ICPU(INTEL_FAM6_SANDYBRIDGE, core_params),
		ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params),
		ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params),
		ICPU(INTEL_FAM6_IVYBRIDGE, core_params),
		ICPU(INTEL_FAM6_HASWELL_CORE, core_params),
		ICPU(INTEL_FAM6_BROADWELL_CORE, core_params),
		ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params),
		ICPU(INTEL_FAM6_HASWELL_X, core_params),
		ICPU(INTEL_FAM6_HASWELL_ULT, core_params),
		ICPU(INTEL_FAM6_HASWELL_GT3E, core_params),
		ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params),
		ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params),
		ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params),
		ICPU(INTEL_FAM6_BROADWELL_X, core_params),
		ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params),
		ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
		ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params),
		{}
		};
		MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);

		static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = {
		ICPU(0x56, core_params),
		ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
		{}
		};