Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 0080d65b authored by Jacob Pan's avatar Jacob Pan Committed by Rafael J. Wysocki
Browse files

idle_intel: Add Denverton 



Denverton is an Intel Atom based micro server which shares the same
Goldmont architecture as Broxton. The available C-states on
Denverton is a subset of Broxton with only C1, C1e, and C6.

Signed-off-by: default avatarJacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: default avatarLen Brown <len.brown@intel.com>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent 02c4fae9

drivers/idle/intel_idle.c

+35 −0
Original line number Diff line number Diff line
@@ -826,6 +826,35 @@ static struct cpuidle_state bxt_cstates[] = { 
		.enter = NULL }

};



static struct cpuidle_state dnv_cstates[] = {

	{

		.name = "C1-DNV",

		.desc = "MWAIT 0x00",

		.flags = MWAIT2flg(0x00),

		.exit_latency = 2,

		.target_residency = 2,

		.enter = &intel_idle,

		.enter_freeze = intel_idle_freeze, },

	{

		.name = "C1E-DNV",

		.desc = "MWAIT 0x01",

		.flags = MWAIT2flg(0x01),

		.exit_latency = 10,

		.target_residency = 20,

		.enter = &intel_idle,

		.enter_freeze = intel_idle_freeze, },

	{

		.name = "C6-DNV",

		.desc = "MWAIT 0x20",

		.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,

		.exit_latency = 50,

		.target_residency = 500,

		.enter = &intel_idle,

		.enter_freeze = intel_idle_freeze, },

	{

		.enter = NULL }

};



/**

 * intel_idle

 * @dev: cpuidle_device
@@ -1015,6 +1044,11 @@ static const struct idle_cpu idle_cpu_bxt = { 
	.disable_promotion_to_c1e = true,

};



static const struct idle_cpu idle_cpu_dnv = {

	.state_table = dnv_cstates,

	.disable_promotion_to_c1e = true,

};



#define ICPU(model, cpu) \

	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
@@ -1051,6 +1085,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = { 
	ICPU(INTEL_FAM6_SKYLAKE_X,		idle_cpu_skx),

	ICPU(INTEL_FAM6_XEON_PHI_KNL,		idle_cpu_knl),

	ICPU(INTEL_FAM6_ATOM_GOLDMONT,		idle_cpu_bxt),

	ICPU(INTEL_FAM6_ATOM_DENVERTON,		idle_cpu_dnv),

	{}

};