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Commit ac85d987 authored by Subbaraman Narayanamurthy's avatar Subbaraman Narayanamurthy
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power: fg-memif: Modify FG SRAM access configuration over DMA 



Currently, when SRAM access over DMA is requested, low latency is
set and it is cleared after SRAM access is done and DMA is
released. Instead of this, keep low latency set always as per the
hardware recommendation. With this, memory arbitration request is
made when SRAM is accessed by software and released when SRAM
access is completed without changing the latency configuration.

Also, change the order of register writes for DMA request and
release as following:

DMA request:
- Memory arbiter request
- Memory interface request

DMA release:
- Memory interface release
- Memory arbiter release

While at it, clear the DMA error log bit during initialization.

Change-Id: I3ddbe9ca6053673c3dc7b1620bed472546278547
Signed-off-by: default avatarSubbaraman Narayanamurthy <subbaram@codeaurora.org>
parent 8dfc046a

drivers/power/supply/qcom/fg-memif.c

+45 −31
Original line number Original line Diff line number Diff line
@@ -793,36 +793,52 @@ int fg_interleaved_mem_write(struct fg_dev *fg, u16 address, u8 offset, 
	return rc;

	return rc;

}

}





#define MEM_GNT_WAIT_TIME_US	10000

static int fg_direct_mem_release(struct fg_dev *fg)

#define MEM_GNT_RETRIES		50

static int fg_direct_mem_request(struct fg_dev *fg, bool request)

{

{

	int rc, ret, i = 0;

	int rc;

	u8 val, mask, poll_bit;

	u8 val = 0, mask;





	mask = MEM_ACCESS_REQ_BIT | IACS_SLCT_BIT;

	mask = MEM_ACCESS_REQ_BIT | IACS_SLCT_BIT;

	val = request ? MEM_ACCESS_REQ_BIT : 0;

	rc = fg_masked_write(fg, MEM_IF_MEM_INTF_CFG(fg), mask, val);

	rc = fg_masked_write(fg, MEM_IF_MEM_INTF_CFG(fg), mask, val);

	if (rc < 0) {

	if (rc < 0) {

		pr_err("failed to configure mem_if_mem_intf_cfg rc=%d\n", rc);

		pr_err("failed to configure mem_if_mem_intf_cfg rc=%d\n", rc);

		return rc;

		return rc;

	}

	}





	mask = MEM_ARB_LO_LATENCY_EN_BIT | MEM_ARB_REQ_BIT;

	mask = MEM_ARB_REQ_BIT;

	val = request ? mask : 0;

	rc = fg_masked_write(fg, MEM_IF_MEM_ARB_CFG(fg), mask, val);

	rc = fg_masked_write(fg, MEM_IF_MEM_ARB_CFG(fg), mask, val);

	if (rc < 0) {

	if (rc < 0) {

		pr_err("failed to configure mem_if_mem_arb_cfg rc:%d\n", rc);

		pr_err("failed to configure mem_if_mem_arb_cfg rc:%d\n", rc);

		return rc;

	}



	pr_debug("released access\n");

	return rc;

}



#define MEM_GNT_WAIT_TIME_US	10000

#define MEM_GNT_RETRIES		50

static int fg_direct_mem_request(struct fg_dev *fg)

{

	int rc, ret, i = 0;

	u8 val, mask, poll_bit;



	val = mask = MEM_ARB_REQ_BIT;

	rc = fg_masked_write(fg, MEM_IF_MEM_ARB_CFG(fg), mask, val);

	if (rc < 0) {

		pr_err("failed to configure mem_if_mem_arb_cfg rc:%d\n", rc);

		return rc;

	}



	mask = MEM_ACCESS_REQ_BIT | IACS_SLCT_BIT;

	val = MEM_ACCESS_REQ_BIT;

	rc = fg_masked_write(fg, MEM_IF_MEM_INTF_CFG(fg), mask, val);

	if (rc < 0) {

		pr_err("failed to configure mem_if_mem_intf_cfg rc=%d\n", rc);

		goto release;

		goto release;

	}

	}





	if (request)

	pr_debug("requesting access\n");

	pr_debug("requesting access\n");

	else

		pr_debug("releasing access\n");



	if (!request)

		return 0;





	/*

	/*

	 * HW takes 5 cycles (200 KHz clock) to grant access after requesting

	 * HW takes 5 cycles (200 KHz clock) to grant access after requesting
@@ -858,20 +874,9 @@ static int fg_direct_mem_request(struct fg_dev *fg, bool request) 
	fg_dump_regs(fg);

	fg_dump_regs(fg);





release:

release:

	val = 0;

	ret = fg_direct_mem_release(fg);

	mask = MEM_ACCESS_REQ_BIT | IACS_SLCT_BIT;

	if (ret < 0)

	ret = fg_masked_write(fg, MEM_IF_MEM_INTF_CFG(fg), mask, val);

	if (ret < 0) {

		pr_err("failed to configure mem_if_mem_intf_cfg rc=%d\n", rc);

		return ret;

		return ret;

	}



	mask = MEM_ARB_LO_LATENCY_EN_BIT | MEM_ARB_REQ_BIT;

	ret = fg_masked_write(fg, MEM_IF_MEM_ARB_CFG(fg), mask, val);

	if (ret < 0) {

		pr_err("failed to configure mem_if_mem_arb_cfg rc:%d\n", rc);

		return ret;

	}





	return rc;

	return rc;

}

}
@@ -987,7 +992,7 @@ static int __fg_direct_mem_rw(struct fg_dev *fg, u16 sram_addr, u8 offset, 




	pr_debug("number of partitions: %d\n", num_partitions);

	pr_debug("number of partitions: %d\n", num_partitions);





	rc = fg_direct_mem_request(fg, true);

	rc = fg_direct_mem_request(fg);

	if (rc < 0) {

	if (rc < 0) {

		pr_err("Error in requesting direct_mem access rc=%d\n", rc);

		pr_err("Error in requesting direct_mem access rc=%d\n", rc);

		return rc;

		return rc;
@@ -1032,7 +1037,7 @@ static int __fg_direct_mem_rw(struct fg_dev *fg, u16 sram_addr, u8 offset, 
		offset = 0;

		offset = 0;

	}

	}





	ret = fg_direct_mem_request(fg, false);

	rc = fg_direct_mem_release(fg);

	if (ret < 0) {

	if (ret < 0) {

		pr_err("Error in releasing direct_mem access rc=%d\n", rc);

		pr_err("Error in releasing direct_mem access rc=%d\n", rc);

		return ret;

		return ret;
@@ -1196,13 +1201,22 @@ static int fg_dma_init(struct fg_dev *fg) 
	}

	}





	/* Release the DMA initially so that request can happen */

	/* Release the DMA initially so that request can happen */

	rc = fg_direct_mem_request(fg, false);

	rc = fg_direct_mem_release(fg);

	if (rc < 0) {

	if (rc < 0) {

		pr_err("Error in releasing direct_mem access rc=%d\n",

		pr_err("Error in releasing direct_mem access rc=%d\n",

			rc);

			rc);

		return rc;

		return rc;

	}

	}





	/* Set low latency always and clear log bit */

	rc = fg_masked_write(fg, MEM_IF_MEM_ARB_CFG(fg),

		MEM_ARB_LO_LATENCY_EN_BIT | MEM_CLR_LOG_BIT,

		MEM_ARB_LO_LATENCY_EN_BIT);

	if (rc < 0) {

		pr_err("failed to configure mem_if_mem_arb_cfg rc:%d\n", rc);

		return rc;

	}



	return 0;

	return 0;

}

}

drivers/power/supply/qcom/fg-reg.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -284,6 +284,7 @@ 
#define GEN4_MEM_ATTN_BIT			BIT(4)

#define GEN4_MEM_ATTN_BIT			BIT(4)





#define MEM_IF_MEM_ARB_CFG(chip)		((chip->mem_if_base) + 0x40)

#define MEM_IF_MEM_ARB_CFG(chip)		((chip->mem_if_base) + 0x40)

#define MEM_CLR_LOG_BIT				BIT(2)

#define MEM_ARB_LO_LATENCY_EN_BIT		BIT(1)

#define MEM_ARB_LO_LATENCY_EN_BIT		BIT(1)

#define MEM_ARB_REQ_BIT				BIT(0)

#define MEM_ARB_REQ_BIT				BIT(0)