power: fg-memif: Modify FG SRAM access configuration over DMA

Currently, when SRAM access over DMA is requested, low latency is
set and it is cleared after SRAM access is done and DMA is
released. Instead of this, keep low latency set always as per the
hardware recommendation. With this, memory arbitration request is
made when SRAM is accessed by software and released when SRAM
access is completed without changing the latency configuration.

Also, change the order of register writes for DMA request and
release as following:

DMA request:
- Memory arbiter request
- Memory interface request

DMA release:
- Memory interface release
- Memory arbiter release

While at it, clear the DMA error log bit during initialization.

Change-Id: I3ddbe9ca6053673c3dc7b1620bed472546278547
Signed-off-by: Subbaraman Narayanamurthy <subbaram@codeaurora.org>