Loading drivers/clk/qcom/gcc-sdmshrike.c +4 −4 Original line number Diff line number Diff line Loading @@ -2690,7 +2690,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0x6b024, .halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(4), Loading Loading @@ -2790,7 +2790,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { static struct clk_branch gcc_pcie_1_pipe_clk = { .halt_reg = 0x8d024, .halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(30), Loading Loading @@ -2877,7 +2877,7 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = { static struct clk_branch gcc_pcie_2_pipe_clk = { .halt_reg = 0x9d024, .halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52014, .enable_mask = BIT(15), Loading Loading @@ -2964,7 +2964,7 @@ static struct clk_branch gcc_pcie_3_mstr_axi_clk = { static struct clk_branch gcc_pcie_3_pipe_clk = { .halt_reg = 0xa3024, .halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52014, .enable_mask = BIT(21), Loading Loading
drivers/clk/qcom/gcc-sdmshrike.c +4 −4 Original line number Diff line number Diff line Loading @@ -2690,7 +2690,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { static struct clk_branch gcc_pcie_0_pipe_clk = { .halt_reg = 0x6b024, .halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x5200c, .enable_mask = BIT(4), Loading Loading @@ -2790,7 +2790,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { static struct clk_branch gcc_pcie_1_pipe_clk = { .halt_reg = 0x8d024, .halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(30), Loading Loading @@ -2877,7 +2877,7 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = { static struct clk_branch gcc_pcie_2_pipe_clk = { .halt_reg = 0x9d024, .halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52014, .enable_mask = BIT(15), Loading Loading @@ -2964,7 +2964,7 @@ static struct clk_branch gcc_pcie_3_mstr_axi_clk = { static struct clk_branch gcc_pcie_3_pipe_clk = { .halt_reg = 0xa3024, .halt_check = BRANCH_HALT_VOTED, .halt_check = BRANCH_HALT_SKIP, .clkr = { .enable_reg = 0x52014, .enable_mask = BIT(21), Loading