Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1d90cf48 authored by Veera Vegivada's avatar Veera Vegivada
Browse files

clk: qcom: gcc: Update halt_check flag for the PCIe pipe clks 



Pipe clocks are sourced from the external PHY, so skip the checking
of the clk_off bit in the halt register.

Change-Id: Ib43ccef47877675cda3cb28134306b5d3efc55a2
Signed-off-by: default avatarVeera Vegivada <vvegivad@codeaurora.org>
parent 2b16b0cf

drivers/clk/qcom/gcc-sdmshrike.c

+4 −4
Original line number Diff line number Diff line
@@ -2690,7 +2690,7 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 


static struct clk_branch gcc_pcie_0_pipe_clk = {

	.halt_reg = 0x6b024,

	.halt_check = BRANCH_HALT_VOTED,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x5200c,

		.enable_mask = BIT(4),
@@ -2790,7 +2790,7 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 


static struct clk_branch gcc_pcie_1_pipe_clk = {

	.halt_reg = 0x8d024,

	.halt_check = BRANCH_HALT_VOTED,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x52004,

		.enable_mask = BIT(30),
@@ -2877,7 +2877,7 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 


static struct clk_branch gcc_pcie_2_pipe_clk = {

	.halt_reg = 0x9d024,

	.halt_check = BRANCH_HALT_VOTED,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x52014,

		.enable_mask = BIT(15),
@@ -2964,7 +2964,7 @@ static struct clk_branch gcc_pcie_3_mstr_axi_clk = { 


static struct clk_branch gcc_pcie_3_pipe_clk = {

	.halt_reg = 0xa3024,

	.halt_check = BRANCH_HALT_VOTED,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x52014,

		.enable_mask = BIT(21),