clk: qcom: mdss: update the names for DP 10nm PLL clocks

Update the clock names for DP PLL and VCO mux clocks to match
with the strings in the DISPCC clock driver for sdmmagpie as
per the clock plan.

Change-Id: I3f23584e8d0188ec5cd012a2bc86e3860739e9fd
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>