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Commit a9d5fcc0 authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Jason Cooper
Browse files

irqchip: dw-apb-ictl: Enable IRQ_GC_MASK_CACHE_PER_TYPE 



The irq_chip_type instances have separate mask registers, so we need to
enable IRQ_GC_MASK_CACHE_PER_TYPE to actually handle separate mask registers.

Signed-off-by: default avatarJisheng Zhang <jszhang@marvell.com>
Acked-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1415773374-4629-3-git-send-email-jszhang@marvell.com


Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 8876ce7d

drivers/irqchip/irq-dw-apb-ictl.c

+1 −0
Original line number Diff line number Diff line
@@ -115,6 +115,7 @@ static int __init dw_apb_ictl_init(struct device_node *np, 


	ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,

					     np->name, handle_level_irq, clr, 0,

					     IRQ_GC_MASK_CACHE_PER_TYPE |

					     IRQ_GC_INIT_MASK_CACHE);

	if (ret) {

		pr_err("%s: unable to alloc irq domain gc\n", np->full_name);