drm/msm: avoid power event setting during mode_2 exit

RSC rev_2 supports 64 bit timer counter and power event
BIT(13) set/reset is not required during mode_2
exit sequence. Update the rsc sequence based revision.

Change-Id: I82428056e0b05136c801de40c73914c022129830
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>