Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Skip to content
Commit a686f70d authored by Xiang Li's avatar Xiang Li
Browse files

ARM: dts: msm: Add tcsr configuration for sa8195p



The TCSR_PCIEPHY_LINK_CONFIG reg is 1 by default. This makes the linkage
status:
PCIe1: not enabled
PCIe2: x4 lane
Setting the reg to 0 changes the status to:
PCIe1: x2 lane
PCIe2: x2 lane
This change add the tcsr configuration for sa8195p and set it to 2x2 lane
mode by default.

Change-Id: Ie789aa7544c94cb207b27847dccefd39d6500280
Signed-off-by: default avatarXiang Li <lixiang@codeaurora.org>
parent dc8ad2e8
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment