Commit a5948fa0 authored Apr 25, 2014 by Alexander Graf

KVM: PPC: Book3S PR: Emulate TIR register



In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
Thread ID Register (TIR). Since PR KVM doesn't emulate more than one thread
per core, we can just always expose 0 here.

Signed-off-by: Alexander Graf <agraf@suse.de>

parent f8f6eb0d

arch/powerpc/kvm/book3s_emulate.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -566,6 +566,7 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu vcpu, int sprn, ulong spr_val
		case SPRN_MMCR0:
		case SPRN_MMCR1:
		case SPRN_MMCR2:
		case SPRN_TIR:
		#endif
		*spr_val = 0;
		break;