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Commit 9837b75e authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes Ide35ef1a,I45eaa51e,I9c7bcdee into msm-next 

* changes:
  clocksource: arch_timer: Use _no_log variants while accessing registers
  irqchip: GICv3: Check if GIC register access is controlled
  drivers: GICv3: Add mb() after the read of GIC registers
parents 4f79eb1c c6ab4979

arch/arm64/include/asm/arch_gicv3.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -79,6 +79,8 @@ static inline u64 gic_read_iar_cavium_thunderx(void) 
static inline void gic_write_pmr(u32 val)

static inline void gic_write_pmr(u32 val)

{

{

	write_sysreg_s(val, SYS_ICC_PMR_EL1);

	write_sysreg_s(val, SYS_ICC_PMR_EL1);

	/* As per the architecture specification */

	mb();

}

}





static inline void gic_write_ctlr(u32 val)

static inline void gic_write_ctlr(u32 val)
@@ -96,6 +98,8 @@ static inline void gic_write_grpen1(u32 val) 
static inline void gic_write_sgi1r(u64 val)

static inline void gic_write_sgi1r(u64 val)

{

{

	write_sysreg_s(val, SYS_ICC_SGI1R_EL1);

	write_sysreg_s(val, SYS_ICC_SGI1R_EL1);

	/* As per the architecture specification */

	mb();

}

}





static inline u32 gic_read_sre(void)

static inline u32 gic_read_sre(void)

drivers/clocksource/arm_arch_timer.c

+12 −12
Original line number Original line Diff line number Diff line
@@ -98,20 +98,20 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val, 
		struct arch_timer *timer = to_arch_timer(clk);

		struct arch_timer *timer = to_arch_timer(clk);

		switch (reg) {

		switch (reg) {

		case ARCH_TIMER_REG_CTRL:

		case ARCH_TIMER_REG_CTRL:

			writel_relaxed(val, timer->base + CNTP_CTL);

			writel_relaxed_no_log(val, timer->base + CNTP_CTL);

			break;

			break;

		case ARCH_TIMER_REG_TVAL:

		case ARCH_TIMER_REG_TVAL:

			writel_relaxed(val, timer->base + CNTP_TVAL);

			writel_relaxed_no_log(val, timer->base + CNTP_TVAL);

			break;

			break;

		}

		}

	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {

	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {

		struct arch_timer *timer = to_arch_timer(clk);

		struct arch_timer *timer = to_arch_timer(clk);

		switch (reg) {

		switch (reg) {

		case ARCH_TIMER_REG_CTRL:

		case ARCH_TIMER_REG_CTRL:

			writel_relaxed(val, timer->base + CNTV_CTL);

			writel_relaxed_no_log(val, timer->base + CNTV_CTL);

			break;

			break;

		case ARCH_TIMER_REG_TVAL:

		case ARCH_TIMER_REG_TVAL:

			writel_relaxed(val, timer->base + CNTV_TVAL);

			writel_relaxed_no_log(val, timer->base + CNTV_TVAL);

			break;

			break;

		}

		}

	} else {

	} else {
@@ -129,20 +129,20 @@ u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, 
		struct arch_timer *timer = to_arch_timer(clk);

		struct arch_timer *timer = to_arch_timer(clk);

		switch (reg) {

		switch (reg) {

		case ARCH_TIMER_REG_CTRL:

		case ARCH_TIMER_REG_CTRL:

			val = readl_relaxed(timer->base + CNTP_CTL);

			val = readl_relaxed_no_log(timer->base + CNTP_CTL);

			break;

			break;

		case ARCH_TIMER_REG_TVAL:

		case ARCH_TIMER_REG_TVAL:

			val = readl_relaxed(timer->base + CNTP_TVAL);

			val = readl_relaxed_no_log(timer->base + CNTP_TVAL);

			break;

			break;

		}

		}

	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {

	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {

		struct arch_timer *timer = to_arch_timer(clk);

		struct arch_timer *timer = to_arch_timer(clk);

		switch (reg) {

		switch (reg) {

		case ARCH_TIMER_REG_CTRL:

		case ARCH_TIMER_REG_CTRL:

			val = readl_relaxed(timer->base + CNTV_CTL);

			val = readl_relaxed_no_log(timer->base + CNTV_CTL);

			break;

			break;

		case ARCH_TIMER_REG_TVAL:

		case ARCH_TIMER_REG_TVAL:

			val = readl_relaxed(timer->base + CNTV_TVAL);

			val = readl_relaxed_no_log(timer->base + CNTV_TVAL);

			break;

			break;

		}

		}

	} else {

	} else {
@@ -869,9 +869,9 @@ static u64 arch_counter_get_cntvct_mem(void) 
	u32 vct_lo, vct_hi, tmp_hi;

	u32 vct_lo, vct_hi, tmp_hi;





	do {

	do {

		vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);

		vct_hi = readl_relaxed_no_log(arch_counter_base + CNTVCT_HI);

		vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);

		vct_lo = readl_relaxed_no_log(arch_counter_base + CNTVCT_LO);

		tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);

		tmp_hi = readl_relaxed_no_log(arch_counter_base + CNTVCT_HI);

	} while (vct_hi != tmp_hi);

	} while (vct_hi != tmp_hi);





	return ((u64) vct_hi << 32) | vct_lo;

	return ((u64) vct_hi << 32) | vct_lo;
@@ -1241,7 +1241,7 @@ arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem) 
		return NULL;

		return NULL;

	}

	}





	cnttidr = readl_relaxed(cntctlbase + CNTTIDR);

	cnttidr = readl_relaxed_no_log(cntctlbase + CNTTIDR);





	/*

	/*

	 * Try to find a virtual capable frame. Otherwise fall back to a

	 * Try to find a virtual capable frame. Otherwise fall back to a

drivers/irqchip/Kconfig

+9 −0
Original line number Original line Diff line number Diff line
@@ -41,6 +41,15 @@ config ARM_GIC_V3_ITS 
	depends on PCI

	depends on PCI

	depends on PCI_MSI

	depends on PCI_MSI





config ARM_GIC_V3_ACL

	bool "GICv3 Access control"

	depends on ARM_GIC_V3

	help

	  Access to GIC ITS address space is controlled by EL2.

	  Kernel has no permission to access GIC ITS address space.

	  If you wish to enforce the Acces control then set this

	  option to Y, if you are unsure please say N.



config ARM_NVIC

config ARM_NVIC

	bool

	bool

	select IRQ_DOMAIN

	select IRQ_DOMAIN

drivers/irqchip/irq-gic-v3.c

+4 −2
Original line number Original line Diff line number Diff line
@@ -538,7 +538,8 @@ static void gic_cpu_init(void) 
	gic_cpu_config(rbase, gic_redist_wait_for_rwp);

	gic_cpu_config(rbase, gic_redist_wait_for_rwp);





	/* Give LPIs a spin */

	/* Give LPIs a spin */

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&

					!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))

		its_cpu_init();

		its_cpu_init();





	/* initialise system registers */

	/* initialise system registers */
@@ -952,7 +953,8 @@ static int __init gic_init_bases(void __iomem *dist_base, 




	set_handle_irq(gic_handle_irq);

	set_handle_irq(gic_handle_irq);





	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis())

	if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() &&

			!IS_ENABLED(CONFIG_ARM_GIC_V3_ACL))

		its_init(handle, &gic_data.rdists, gic_data.domain);

		its_init(handle, &gic_data.rdists, gic_data.domain);





	gic_smp_init();

	gic_smp_init();