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Commit 97af8838 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: sm6150: Update pll ops for all clock controllers"

parents edcb7d55 627c4a1e

drivers/clk/qcom/camcc-sm6150.c

+15 −12
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -149,13 +149,16 @@ static const char * const cam_cc_parent_names_6[] = { 
	"core_bi_pll_test_se",

};



static struct pll_vco cam_cc_pll0_vco[] = {

	{ 500000000, 1000000000, 2 },

};



static struct pll_vco cam_cc_pll2_vco[] = {

	{ 500000000, 1250000000, 0 },

};



static struct pll_vco cam_cc_pll_vco[] = {

static struct pll_vco cam_cc_pll3_vco[] = {

	{ 1000000000, 2000000000, 0 },

	{ 500000000, 1000000000, 2 },

};



/* 600MHz configuration */
@@ -173,15 +176,15 @@ static struct alpha_pll_config cam_cc_pll0_config = { 


static struct clk_alpha_pll cam_cc_pll0_out_aux = {

	.offset = 0x0,

	.vco_table = cam_cc_pll_vco,

	.num_vco = ARRAY_SIZE(cam_cc_pll_vco),

	.vco_table = cam_cc_pll0_vco,

	.num_vco = ARRAY_SIZE(cam_cc_pll0_vco),

	.config = &cam_cc_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll0_out_aux",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_alpha_pll_ops,

			.ops = &clk_alpha_pll_slew_ops,

			.vdd_class = &vdd_cx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {
@@ -207,15 +210,15 @@ static struct alpha_pll_config cam_cc_pll1_config = { 


static struct clk_alpha_pll cam_cc_pll1_out_aux = {

	.offset = 0x1000,

	.vco_table = cam_cc_pll_vco,

	.num_vco = ARRAY_SIZE(cam_cc_pll_vco),

	.vco_table = cam_cc_pll0_vco,

	.num_vco = ARRAY_SIZE(cam_cc_pll0_vco),

	.config = &cam_cc_pll1_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll1_out_aux",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_alpha_pll_ops,

			.ops = &clk_alpha_pll_slew_ops,

			.vdd_class = &vdd_cx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {
@@ -284,15 +287,15 @@ static struct alpha_pll_config cam_cc_pll3_config = { 


static struct clk_alpha_pll cam_cc_pll3_out_main = {

	.offset = 0x3000,

	.vco_table = cam_cc_pll_vco,

	.num_vco = ARRAY_SIZE(cam_cc_pll_vco),

	.vco_table = cam_cc_pll3_vco,

	.num_vco = ARRAY_SIZE(cam_cc_pll3_vco),

	.config = &cam_cc_pll3_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll3_out_main",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_alpha_pll_ops,

			.ops = &clk_alpha_pll_slew_ops,

			.vdd_class = &vdd_mx,

			.num_rate_max = VDD_MX_NUM,

			.rate_max = (unsigned long[VDD_MX_NUM]) {

drivers/clk/qcom/dispcc-sm6150.c

+2 −15
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -139,18 +139,6 @@ static struct alpha_pll_config disp_cc_pll0_config = { 
	.test_ctl_hi_mask = 0x1,

};



static struct clk_init_data disp_cc_pll0_out_main_sa6155 = {

	.name = "disp_cc_pll0_out_main",

	.parent_names = (const char *[]){ "bi_tcxo" },

	.num_parents = 1,

	.ops = &clk_alpha_pll_slew_ops,

	.vdd_class = &vdd_cx,

	.num_rate_max = VDD_NUM,

	.rate_max = (unsigned long[VDD_NUM]) {

		[VDD_MIN] = 1000000000,

		[VDD_NOMINAL] = 2000000000},

};



static struct clk_alpha_pll disp_cc_pll0_out_main = {

	.offset = 0x0,

	.vco_table = disp_cc_pll_vco,
@@ -162,7 +150,7 @@ static struct clk_alpha_pll disp_cc_pll0_out_main = { 
			.name = "disp_cc_pll0_out_main",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_alpha_pll_ops,

			.ops = &clk_alpha_pll_slew_ops,

			.vdd_class = &vdd_cx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {
@@ -837,7 +825,6 @@ static void dispcc_sm6150_fixup_sa6155(struct platform_device *pdev) 
{

	vdd_cx.num_levels = VDD_NUM_SA6155;

	vdd_cx.cur_level = VDD_NUM_SA6155;

	disp_cc_pll0_out_main.clkr.hw.init = &disp_cc_pll0_out_main_sa6155;

}



static int disp_cc_sm6150_probe(struct platform_device *pdev)

drivers/clk/qcom/gpucc-sm6150.c

+7 −43
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -96,11 +96,6 @@ static const char * const gpu_cc_parent_names_1[] = { 
	"core_bi_pll_test_se",

};



static struct pll_vco gpu_cc_pll_vco[] = {

	{ 1000000000, 2000000000, 0 },

	{ 500000000,  1000000000, 2 },

};



static struct pll_vco gpu_cc_pll0_vco[] = {

	{ 1000000000, 2000000000, 0 },

};
@@ -137,22 +132,10 @@ static struct alpha_pll_config gpu_pll1_config = { 
	.aux2_output_mask = BIT(2),

};



static struct clk_init_data gpu_cc_pll0_out_aux2_sa6155 = {

	.name = "gpu_cc_pll0_out_aux2",

	.parent_names = (const char *[]){ "bi_tcxo" },

	.num_parents = 1,

	.ops = &clk_alpha_pll_slew_ops,

	.vdd_class = &vdd_mx,

	.num_rate_max = VDD_MX_NUM,

	.rate_max = (unsigned long[VDD_MX_NUM]) {

		[VDD_MX_MIN] = 1000000000,

		[VDD_MX_NOMINAL] = 2000000000},

};



static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = {

	.offset = 0x0,

	.vco_table = gpu_cc_pll_vco,

	.num_vco = ARRAY_SIZE(gpu_cc_pll_vco),

	.vco_table = gpu_cc_pll0_vco,

	.num_vco = ARRAY_SIZE(gpu_cc_pll0_vco),

	.flags = SUPPORTS_DYNAMIC_UPDATE,

	.config = &gpu_pll0_config,

	.clkr = {
@@ -160,7 +143,7 @@ static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = { 
		.name = "gpu_cc_pll0_out_aux2",

		.parent_names = (const char *[]){ "bi_tcxo" },

		.num_parents = 1,

		.ops = &clk_alpha_pll_ops,

		.ops = &clk_alpha_pll_slew_ops,

		.vdd_class = &vdd_mx,

		.num_rate_max = VDD_MX_NUM,

		.rate_max = (unsigned long[VDD_MX_NUM]) {
@@ -170,22 +153,10 @@ static struct clk_alpha_pll gpu_cc_pll0_out_aux2 = { 
	},

};



static struct clk_init_data gpu_cc_pll1_out_aux2_sa6155 = {

	.name = "gpu_cc_pll1_out_aux2",

	.parent_names = (const char *[]){ "bi_tcxo" },

	.num_parents = 1,

	.ops = &clk_alpha_pll_slew_ops,

	.vdd_class = &vdd_mx,

	.num_rate_max = VDD_MX_NUM,

	.rate_max = (unsigned long[VDD_MX_NUM]) {

		[VDD_MX_MIN] = 1000000000,

		[VDD_MX_NOMINAL] = 2000000000},

};



static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = {

	.offset = 0x100,

	.vco_table = gpu_cc_pll_vco,

	.num_vco = ARRAY_SIZE(gpu_cc_pll_vco),

	.vco_table = gpu_cc_pll1_vco,

	.num_vco = ARRAY_SIZE(gpu_cc_pll1_vco),

	.flags = SUPPORTS_DYNAMIC_UPDATE,

	.config = &gpu_pll1_config,

	.clkr = {
@@ -193,7 +164,7 @@ static struct clk_alpha_pll gpu_cc_pll1_out_aux2 = { 
		.name = "gpu_cc_pll1_out_aux2",

		.parent_names = (const char *[]){ "bi_tcxo" },

		.num_parents = 1,

		.ops = &clk_alpha_pll_ops,

		.ops = &clk_alpha_pll_slew_ops,

		.vdd_class = &vdd_mx,

		.num_rate_max = VDD_MX_NUM,

		.rate_max = (unsigned long[VDD_MX_NUM]) {
@@ -597,13 +568,6 @@ static void gpucc_sm6150_fixup_sa6155(struct platform_device *pdev) 
	vdd_mx.cur_level = VDD_MX_NUM_SA6155;

	gpu_cc_gx_gfx3d_clk_src.clkr.hw.init->rate_max[VDD_HIGH_L1] = 0;

	gpu_cc_gx_gfx3d_clk_src.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src_sa6155;



	gpu_cc_pll0_out_aux2.vco_table = gpu_cc_pll0_vco;

	gpu_cc_pll0_out_aux2.num_vco = ARRAY_SIZE(gpu_cc_pll0_vco);

	gpu_cc_pll0_out_aux2.clkr.hw.init = &gpu_cc_pll0_out_aux2_sa6155;

	gpu_cc_pll1_out_aux2.vco_table = gpu_cc_pll1_vco;

	gpu_cc_pll1_out_aux2.num_vco = ARRAY_SIZE(gpu_cc_pll1_vco);

	gpu_cc_pll1_out_aux2.clkr.hw.init = &gpu_cc_pll1_out_aux2_sa6155;

	pdev->dev.driver->pm =  &gpu_cc_sm6150_pm_ops;

}

drivers/clk/qcom/videocc-sm6150.c

+2 −15
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -98,18 +98,6 @@ static struct alpha_pll_config video_pll0_config = { 
	.test_ctl_hi_mask = 0x1,

};



static struct clk_init_data video_pll0_out_main_sa6155 = {

	.name = "video_pll0_out_main",

	.parent_names = (const char *[]){ "bi_tcxo" },

	.num_parents = 1,

	.ops = &clk_alpha_pll_slew_ops,

	.vdd_class = &vdd_cx,

	.num_rate_max = VDD_NUM,

	.rate_max = (unsigned long[VDD_NUM]) {

		[VDD_MIN] = 1000000000,

		[VDD_NOMINAL] = 2000000000},

};



static struct clk_alpha_pll video_pll0_out_main = {

	.offset = 0x42c,

	.vco_table = video_cc_pll_vco,
@@ -121,7 +109,7 @@ static struct clk_alpha_pll video_pll0_out_main = { 
			.name = "video_pll0_out_main",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_alpha_pll_ops,

			.ops = &clk_alpha_pll_slew_ops,

			.vdd_class = &vdd_cx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {
@@ -369,7 +357,6 @@ static void videocc_sm6150_fixup_sa6155(struct platform_device *pdev) 
	vdd_cx.num_levels = VDD_NUM_SA6155;

	vdd_cx.cur_level = VDD_NUM_SA6155;



	video_pll0_out_main.clkr.hw.init = &video_pll0_out_main_sa6155,

	pdev->dev.driver->pm =  &video_cc_sa6150_pm_ops;

}