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Commit 90e68720 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.14-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC fixes from Vineet Gupta:

 - Fixes for HSDK platform

 - module build error for !LLSC config

* tag 'arc-4.14-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: unbork module link errors with !CONFIG_ARC_HAS_LLSC
  ARC: [plat-hsdk] Increase SDIO CIU frequency to 50000000Hz
  ARC: [plat-hsdk] select CONFIG_RESET_HSDK from Kconfig
parents a0cb2b5c fdbed196

arch/arc/boot/dts/hsdk.dts

+6 −5
Original line number Original line Diff line number Diff line
@@ -137,14 +137,15 @@ 
			/*

			/*

			 * DW sdio controller has external ciu clock divider

			 * DW sdio controller has external ciu clock divider

			 * controlled via register in SDIO IP. Due to its

			 * controlled via register in SDIO IP. Due to its

			 * unexpected default value (it should devide by 1

			 * unexpected default value (it should divide by 1

			 * but it devides by 8) SDIO IP uses wrong clock and

			 * but it divides by 8) SDIO IP uses wrong clock and

			 * works unstable (see STAR 9001204800)

			 * works unstable (see STAR 9001204800)

			 * We switched to the minimum possible value of the

			 * divisor (div-by-2) in HSDK platform code.

			 * So add temporary fix and change clock frequency

			 * So add temporary fix and change clock frequency

			 * from 100000000 to 12500000 Hz until we fix dw sdio

			 * to 50000000 Hz until we fix dw sdio driver itself.

			 * driver itself.

			 */

			 */

			clock-frequency = <12500000>;

			clock-frequency = <50000000>;

			#clock-cells = <0>;

			#clock-cells = <0>;

		};

		};

arch/arc/configs/hsdk_defconfig

+0 −1
Original line number Original line Diff line number Diff line
@@ -63,7 +63,6 @@ CONFIG_MMC_SDHCI=y 
CONFIG_MMC_SDHCI_PLTFM=y

CONFIG_MMC_SDHCI_PLTFM=y

CONFIG_MMC_DW=y

CONFIG_MMC_DW=y

# CONFIG_IOMMU_SUPPORT is not set

# CONFIG_IOMMU_SUPPORT is not set

CONFIG_RESET_HSDK=y

CONFIG_EXT3_FS=y

CONFIG_EXT3_FS=y

CONFIG_VFAT_FS=y

CONFIG_VFAT_FS=y

CONFIG_TMPFS=y

CONFIG_TMPFS=y

arch/arc/kernel/smp.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -23,6 +23,8 @@ 
#include <linux/cpumask.h>

#include <linux/cpumask.h>

#include <linux/reboot.h>

#include <linux/reboot.h>

#include <linux/irqdomain.h>

#include <linux/irqdomain.h>

#include <linux/export.h>



#include <asm/processor.h>

#include <asm/processor.h>

#include <asm/setup.h>

#include <asm/setup.h>

#include <asm/mach_desc.h>

#include <asm/mach_desc.h>
@@ -30,6 +32,9 @@ 
#ifndef CONFIG_ARC_HAS_LLSC

#ifndef CONFIG_ARC_HAS_LLSC

arch_spinlock_t smp_atomic_ops_lock = __ARCH_SPIN_LOCK_UNLOCKED;

arch_spinlock_t smp_atomic_ops_lock = __ARCH_SPIN_LOCK_UNLOCKED;

arch_spinlock_t smp_bitops_lock = __ARCH_SPIN_LOCK_UNLOCKED;

arch_spinlock_t smp_bitops_lock = __ARCH_SPIN_LOCK_UNLOCKED;



EXPORT_SYMBOL_GPL(smp_atomic_ops_lock);

EXPORT_SYMBOL_GPL(smp_bitops_lock);

#endif

#endif





struct plat_smp_ops  __weak plat_smp_ops;

struct plat_smp_ops  __weak plat_smp_ops;

arch/arc/plat-hsdk/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -8,3 +8,4 @@ 
menuconfig ARC_SOC_HSDK

menuconfig ARC_SOC_HSDK

	bool "ARC HS Development Kit SOC"

	bool "ARC HS Development Kit SOC"

	select CLK_HSDK

	select CLK_HSDK

	select RESET_HSDK

arch/arc/plat-hsdk/platform.c

+10 −0
Original line number Original line Diff line number Diff line
@@ -74,6 +74,10 @@ static void __init hsdk_set_cpu_freq_1ghz(void) 
		pr_err("Failed to setup CPU frequency to 1GHz!");

		pr_err("Failed to setup CPU frequency to 1GHz!");

}

}





#define SDIO_BASE		(ARC_PERIPHERAL_BASE + 0xA000)

#define SDIO_UHS_REG_EXT	(SDIO_BASE + 0x108)

#define SDIO_UHS_REG_EXT_DIV_2	(2 << 30)



static void __init hsdk_init_early(void)

static void __init hsdk_init_early(void)

{

{

	/*

	/*
@@ -89,6 +93,12 @@ static void __init hsdk_init_early(void) 
	/* Really apply settings made above */

	/* Really apply settings made above */

	writel(1, (void __iomem *) CREG_PAE_UPDATE);

	writel(1, (void __iomem *) CREG_PAE_UPDATE);





	/*

	 * Switch SDIO external ciu clock divider from default div-by-8 to

	 * minimum possible div-by-2.

	 */

	iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);



	/*

	/*

	 * Setup CPU frequency to 1GHz.

	 * Setup CPU frequency to 1GHz.

	 * TODO: remove it after smart hsdk pll driver will be introduced.

	 * TODO: remove it after smart hsdk pll driver will be introduced.