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Commit 8ea2f135 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: scc-sm8150: update PLL and RCG clock configurations"

parents 4d994b72 9d6a1e4b

drivers/clk/qcom/scc-sm8150.c

+2 −9
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ static const struct alpha_pll_config scc_pll_config = { 
	.test_ctl_val = 0x00000000,

	.test_ctl_hi_val = 0x00000002,

	.test_ctl_hi1_val = 0x00000000,

	.user_ctl_val = 0x00000000,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x000000D0,

};
@@ -95,7 +95,7 @@ static const struct alpha_pll_config scc_pll_config_sm8150_v2 = { 
	.config_ctl_val = 0x20485699,

	.config_ctl_hi_val = 0x00002267,

	.config_ctl_hi1_val = 0x00000024,

	.user_ctl_val = 0x00000000,

	.user_ctl_val = 0x00000100,

	.user_ctl_hi_val = 0x00000805,

	.user_ctl_hi1_val = 0x000000D0,

};
@@ -164,7 +164,6 @@ static struct clk_rcg2 scc_main_rcg_clk_src = { 
		.name = "scc_main_rcg_clk_src",

		.parent_names = scc_parent_names_0,

		.num_parents = 8,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_scc_cx,

		.num_rate_max = VDD_NUM,
@@ -223,7 +222,6 @@ static struct clk_rcg2 scc_qupv3_se0_clk_src = { 
		.name = "scc_qupv3_se0_clk_src",

		.parent_names = scc_parent_names_0,

		.num_parents = 8,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_scc_cx,

		.num_rate_max = VDD_NUM,
@@ -245,7 +243,6 @@ static struct clk_rcg2 scc_qupv3_se1_clk_src = { 
		.name = "scc_qupv3_se1_clk_src",

		.parent_names = scc_parent_names_0,

		.num_parents = 8,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_scc_cx,

		.num_rate_max = VDD_NUM,
@@ -267,7 +264,6 @@ static struct clk_rcg2 scc_qupv3_se2_clk_src = { 
		.name = "scc_qupv3_se2_clk_src",

		.parent_names = scc_parent_names_0,

		.num_parents = 8,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_scc_cx,

		.num_rate_max = VDD_NUM,
@@ -289,7 +285,6 @@ static struct clk_rcg2 scc_qupv3_se3_clk_src = { 
		.name = "scc_qupv3_se3_clk_src",

		.parent_names = scc_parent_names_0,

		.num_parents = 8,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_scc_cx,

		.num_rate_max = VDD_NUM,
@@ -311,7 +306,6 @@ static struct clk_rcg2 scc_qupv3_se4_clk_src = { 
		.name = "scc_qupv3_se4_clk_src",

		.parent_names = scc_parent_names_0,

		.num_parents = 8,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_scc_cx,

		.num_rate_max = VDD_NUM,
@@ -333,7 +327,6 @@ static struct clk_rcg2 scc_qupv3_se5_clk_src = { 
		.name = "scc_qupv3_se5_clk_src",

		.parent_names = scc_parent_names_0,

		.num_parents = 8,

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		.vdd_class = &vdd_scc_cx,

		.num_rate_max = VDD_NUM,