clk: qcom: scc-sm8150: update PLL and RCG clock configurations
Change the scc_pll configurations to correctly use a post-div of
2 for scc_pll_out_even. Also remove the CLK_SET_RATE_PARENT flag
for all RCGs since their parent PLLs all have fixed rates.
Change-Id: I9105f55ddeace91e6940f0e9cd5c08383e33c5f5
Signed-off-by:
David Collins <collinsd@codeaurora.org>
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