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Commit 897efe62 authored by Yaniv Gardi's avatar Yaniv Gardi Committed by Martin K. Petersen
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scsi: ufs: add missing memory barriers



Performing several writes to UFS host controller registers has no
guarantee of ordering, so we must make sure register writes to setup
request list base address etc. are performed before the run/stop
register is enabled.  In addition, when setting up a task request, we
must make sure the updating of descriptors takes places before ringing
the doorbell, similarly to setting up a transfer request.

Reviewed-by: default avatarDolev Raviv <draviv@codeaurora.org>
Signed-off-by: default avatarGilad Broner <gbroner@codeaurora.org>
Signed-off-by: default avatarYaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent d75f7fe4
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