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Commit 8600b697 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'i2c/for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux 

Pull i2c updates from Wolfram Sang:

 - the first series of making i2c_device_id optional instead of
   mandatory (in favor of alternatives like of_device_id).

   This involves adding a new probe callback (probe_new) which removes
   some peculiarities I2C had for a long time now. The new probe is
   matching the other subsystems now and the old one will be removed
   once all users are converted. It is expected to take a while but
   there is ongoing interest in that.

 - SMBus Host Notify introduced 4.9 got refactored. They are now using
   interrupts instead of the alert callback which solves multiple
   issues.

 - new drivers for iMX LowPower I2C, Mellanox CPLD and its I2C mux

 - significant refactoring for bcm2835 driver

 - the usual set of driver updates and improvements

* 'i2c/for-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (46 commits)
  i2c: fsl-lpi2c: read lpi2c fifo size in probe()
  i2c: octeon: thunderx: Remove double-check after interrupt
  i2c: octeon: thunderx: TWSI software reset in recovery
  i2c: cadence: Allow Cadence I2C to be selected for Cadence Xtensa CPUs
  i2c: sh_mobile: Add per-Generation fallback bindings
  i2c: rcar: Add per-Generation fallback bindings
  i2c: imx-lpi2c: add low power i2c bus driver
  dt-bindings: i2c: imx-lpi2c: add devicetree bindings
  i2c: designware-pcidrv: Add 10bit address feature to medfield/merrifield
  i2c: pxa: Add support for the I2C units found in Armada 3700
  i2c: pxa: Add definition of fast and high speed modes via the regs layout
  dt-bindings: i2c: pxa: Update the documentation for the Armada 3700
  i2c: qup: support SMBus block read
  i2c: qup: add ACPI support
  i2c: designware: Consolidate default functionality bits
  i2c: i2c-mux-gpio: update mux with gpiod_set_array_value_cansleep
  i2c: mux: pca954x: Add ACPI support for pca954x
  i2c: use an IRQ to report Host Notify events, not alert
  i2c: i801: remove SMBNTFDDAT reads as they always seem to return 0
  i2c: i801: use the BIT() macro for FEATURES_* also
  ...
parents 0ab7b12c 6eb89ef0

Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.txt

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* Freescale Low Power Inter IC (LPI2C) for i.MX



Required properties:

- compatible :

  - "fsl,imx7ulp-lpi2c" for LPI2C compatible with the one integrated on i.MX7ULP soc

  - "fsl,imx8dv-lpi2c" for LPI2C compatible with the one integrated on i.MX8DV soc

- reg : address and length of the lpi2c master registers

- interrupt-parent : core interrupt controller

- interrupts : lpi2c interrupt

- clocks : lpi2c clock specifier



Examples:



lpi2c7: lpi2c7@40A50000 {

	compatible = "fsl,imx8dv-lpi2c";

	reg = <0x40A50000 0x10000>;

	interrupt-parent = <&intc>;

	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&clks IMX7ULP_CLK_LPI2C7>;

};

Documentation/devicetree/bindings/i2c/i2c-pxa.txt

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@@ -7,6 +7,7 @@ Required properties : 
   compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.

   For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required

   as shown in the example below.

   For the Armada 3700, the compatible should be "marvell,armada-3700-i2c".



Recommended properties :

Documentation/devicetree/bindings/i2c/i2c-rcar.txt

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I2C for R-Car platforms



Required properties:

- compatible: Must be one of

	"renesas,i2c-rcar"

	"renesas,i2c-r8a7778"

	"renesas,i2c-r8a7779"

	"renesas,i2c-r8a7790"

	"renesas,i2c-r8a7791"

	"renesas,i2c-r8a7792"

	"renesas,i2c-r8a7793"

	"renesas,i2c-r8a7794"

	"renesas,i2c-r8a7795"

	"renesas,i2c-r8a7796"

- compatible:

	"renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.

	"renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.

	"renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.

	"renesas,i2c-r8a7791" if the device is a part of a R8A7791 SoC.

	"renesas,i2c-r8a7792" if the device is a part of a R8A7792 SoC.

	"renesas,i2c-r8a7793" if the device is a part of a R8A7793 SoC.

	"renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.

	"renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.

	"renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.

	"renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.

	"renesas,rcar-gen2-i2c" for a generic R-Car Gen2 compatible device.

	"renesas,rcar-gen3-i2c" for a generic R-Car Gen3 compatible device.

	"renesas,i2c-rcar" (deprecated)



	When compatible with the generic version, nodes must list the

	SoC-specific version corresponding to the platform first followed

	by the generic version.



- reg: physical base address of the controller and length of memory mapped

  region.

- interrupts: interrupt specifier.
@@ -33,7 +41,7 @@ Examples : 
i2c0: i2c@e6508000 {

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "renesas,i2c-r8a7791";

	compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";

	reg = <0 0xe6508000 0 0x40>;

	interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&mstp9_clks R8A7791_CLK_I2C0>;

Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt

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Device tree configuration for Renesas IIC (sh_mobile) driver



Required properties:

- compatible      : "renesas,iic-<soctype>". "renesas,rmobile-iic" as fallback

		     Examples with soctypes are:

- compatible      :

			- "renesas,iic-r8a73a4" (R-Mobile APE6)

			- "renesas,iic-r8a7740" (R-Mobile A1)

			- "renesas,iic-r8a7790" (R-Car H2)
@@ -12,6 +11,17 @@ Required properties: 
			- "renesas,iic-r8a7794" (R-Car E2)

			- "renesas,iic-r8a7795" (R-Car H3)

			- "renesas,iic-sh73a0" (SH-Mobile AG5)

			- "renesas,rcar-gen2-iic" (generic R-Car Gen2 compatible device)

			- "renesas,rcar-gen3-iic" (generic R-Car Gen3 compatible device)

			- "renesas,rmobile-iic" (generic device)



			When compatible with a generic R-Car version, nodes

			must list the SoC-specific version corresponding to

			the platform first followed by the generic R-Car

			version.



			renesas,rmobile-iic must always follow.



- reg             : address start and address range size of device

- interrupts      : interrupt of device

- clocks          : clock for device
@@ -31,7 +41,8 @@ Pinctrl properties might be needed, too. See there. 
Example:



	iic0: i2c@e6500000 {

		compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";

		compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",

			     "renesas,rmobile-iic";

		reg = <0 0xe6500000 0 0x425>;

		interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp3_clks R8A7790_CLK_IIC0>;

Documentation/i2c/busses/i2c-mlxcpld

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Driver i2c-mlxcpld



Author: Michael Shych <michaelsh@mellanox.com>



This is the Mellanox I2C controller logic, implemented in Lattice CPLD

device.

Device supports:

 - Master mode.

 - One physical bus.

 - Polling mode.



This controller is equipped within the next Mellanox systems:

"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800",

"msn2740", "msn2100".



The next transaction types are supported:

 - Receive Byte/Block.

 - Send Byte/Block.

 - Read Byte/Block.

 - Write Byte/Block.



Registers:

CTRL		0x1 - control reg.

			Resets all the registers.

HALF_CYC	0x4 - cycle reg.

			Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK

			units).

I2C_HOLD	0x5 - hold reg.

			OE (output enable) is delayed by value set to this register

			(in LPC_CLK units)

CMD			0x6 - command reg.

			Bit 0, 0 = write, 1 = read.

			Bits [7:1] - the 7bit Address of the I2C device.

			It should be written last as it triggers an I2C transaction.

NUM_DATA	0x7 - data size reg.

			Number of data bytes to write in read transaction

NUM_ADDR	0x8 - address reg.

			Number of address bytes to write in read transaction.

STATUS		0x9 - status reg.

			Bit 0 - transaction is completed.

			Bit 4 - ACK/NACK.

DATAx		0xa - 0x54  - 68 bytes data buffer regs.

			For write transaction address is specified in four first bytes

			(DATA1 - DATA4), data starting from DATA4.

			For read transactions address is sent in a separate transaction and

			specified in the four first bytes (DATA0 - DATA3). Data is read

			starting from DATA0.