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Commit 0ab7b12c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pci-v4.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 

Pull PCI updates from Bjorn Helgaas:
 "PCI changes:

   - add support for PCI on ARM64 boxes with ACPI. We already had this
     for theoretical spec-compliant hardware; now we're adding quirks
     for the actual hardware (Cavium, HiSilicon, Qualcomm, X-Gene)

   - add runtime PM support for hotplug ports

   - enable runtime suspend for Intel UHCI that uses platform-specific
     wakeup signaling

   - add yet another host bridge registration interface. We hope this is
     extensible enough to subsume the others

   - expose device revision in sysfs for DRM

   - to avoid device conflicts, make sure any VF BAR updates are done
     before enabling the VF

   - avoid unnecessary link retrains for ASPM

   - allow INTx masking on Mellanox devices that support it

   - allow access to non-standard VPD for Chelsio devices

   - update Broadcom iProc support for PAXB v2, PAXC v2, inbound DMA,
     etc

   - update Rockchip support for max-link-speed

   - add NVIDIA Tegra210 support

   - add Layerscape LS1046a support

   - update R-Car compatibility strings

   - add Qualcomm MSM8996 support

   - remove some uninformative bootup messages"

* tag 'pci-v4.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (115 commits)
  PCI: Enable access to non-standard VPD for Chelsio devices (cxgb3)
  PCI: Expand "VPD access disabled" quirk message
  PCI: pciehp: Remove loading message
  PCI: hotplug: Remove hotplug core message
  PCI: Remove service driver load/unload messages
  PCI/AER: Log AER IRQ when claiming Root Port
  PCI/AER: Log errors with PCI device, not PCIe service device
  PCI/AER: Remove unused version macros
  PCI/PME: Log PME IRQ when claiming Root Port
  PCI/PME: Drop unused support for PMEs from Root Complex Event Collectors
  PCI: Move config space size macros to pci_regs.h
  x86/platform/intel-mid: Constify mid_pci_platform_pm
  PCI/ASPM: Don't retrain link if ASPM not possible
  PCI: iproc: Skip check for legacy IRQ on PAXC buses
  PCI: pciehp: Leave power indicator on when enabling already-enabled slot
  PCI: pciehp: Prioritize data-link event over presence detect
  PCI: rcar: Add gen3 fallback compatibility string for pcie-rcar
  PCI: rcar: Use gen2 fallback compatibility last
  PCI: rcar-gen2: Use gen2 fallback compatibility last
  PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init()
  ..
parents a9a16a6d b08d2e61

Documentation/ABI/testing/sysfs-bus-pci

+7 −0
Original line number Diff line number Diff line
@@ -294,3 +294,10 @@ Description: 
		a firmware bug to the system vendor.  Writing to this file

		taints the kernel with TAINT_FIRMWARE_WORKAROUND, which

		reduces the supportability of your system.



What:		/sys/bus/pci/devices/.../revision

Date:		November 2016

Contact:	Emil Velikov <emil.l.velikov@gmail.com>

Description:

		This file contains the revision field of the the PCI device.

		The value comes from device config space. The file is read only.

Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt

+28 −15
Original line number Diff line number Diff line 
* Broadcom iProc PCIe controller with the platform bus interface



Required properties:

- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc"

  for PAXC.  PAXB-based root complex is used for external endpoint devices.

  PAXC-based root complex is connected to emulated endpoint devices

  internal to the ASIC

- compatible:

      "brcm,iproc-pcie" for the first generation of PAXB based controller,

used in SoCs including NSP, Cygnus, NS2, and Pegasus

      "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based

controllers, used in Stingray

      "brcm,iproc-pcie-paxc" for the first generation of PAXC based

controller, used in NS2

      "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based

controller, used in Stingray

  PAXB-based root complex is used for external endpoint devices. PAXC-based

root complex is connected to emulated endpoint devices internal to the ASIC

- reg: base address and length of the PCIe controller I/O register space

- #interrupt-cells: set to <1>

- interrupt-map-mask and interrupt-map, standard PCI properties to define the
@@ -19,6 +26,10 @@ Required properties: 
Optional properties:

- phys: phandle of the PCIe PHY device

- phy-names: must be "pcie-phy"

- dma-coherent: present if DMA operations are coherent

- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done

  by the ASIC after power on reset.  In this case, SW is required to configure

the mapping, based on inbound memory regions specified by this property.



- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done

by the ASIC after power on reset. In this case, SW needs to configure it
@@ -29,11 +40,6 @@ effective: 
Required:

- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal

address used by the iProc PCIe core (not the PCIe address)

- brcm,pcie-ob-window-size: The outbound address mapping window size (in MB)



Optional:

- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to

increase the outbound window size



MSI support (optional):
@@ -41,10 +47,19 @@ For older platforms without MSI integrated in the GIC, iProc PCIe core provides 
an event queue based MSI support.  The iProc MSI uses host memories to store

MSI posted writes in the event queues



- msi-parent: Link to the device node of the MSI controller.  On newer iProc

platforms, the MSI controller may be gicv2m or gicv3-its.  On older iProc

platforms without MSI support in its interrupt controller, one may use the

event queue based MSI support integrated within the iProc PCIe core.

On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used



- msi-map: Maps a Requester ID to an MSI controller and associated MSI

sideband data



- msi-parent: Link to the device node of the MSI controller, used when no MSI

sideband data is passed between the iProc PCIe controller and the MSI

controller



Refer to the following binding documents for more detailed description on

the use of 'msi-map' and 'msi-parent':

  Documentation/devicetree/bindings/pci/pci-msi.txt

  Documentation/devicetree/bindings/interrupt-controller/msi.txt



When the iProc event queue based MSI is used, one needs to define the

following properties in the MSI device node:
@@ -80,9 +95,7 @@ Example: 
		phy-names = "pcie-phy";



		brcm,pcie-ob;

		brcm,pcie-ob-oarr-size;

		brcm,pcie-ob-axi-offset = <0x00000000>;

		brcm,pcie-ob-window-size = <256>;



		msi-parent = <&msi0>;

Documentation/devicetree/bindings/pci/layerscape-pci.txt

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Required properties: 
- compatible: should contain the platform identifier such as:

        "fsl,ls1021a-pcie", "snps,dw-pcie"

        "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"

        "fsl,ls1046a-pcie"

- reg: base addresses and lengths of the PCIe controller

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

+110 −0
Original line number Diff line number Diff line
@@ -110,6 +110,20 @@ Power supplies for Tegra124: 
  - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must

    supply 1.05 V.



Power supplies for Tegra210:

- Required:

  - avdd-pll-uerefe-supply: Power supply for PLLE (shared with USB3). Must

    supply 1.05 V.

  - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output

    clocks. Must supply 1.8 V.

  - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.

  - dvdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must

    supply 1.05 V.

  - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).

    Must supply 3.3 V.

  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must

    supply 1.8 V.



Root ports are defined as subnodes of the PCIe controller node.



Required properties:
@@ -436,3 +450,99 @@ Board DTS: 
			status = "okay";

		};

	};



Tegra210:

---------



SoC DTSI:



	pcie-controller@01003000 {

		compatible = "nvidia,tegra210-pcie";

		device_type = "pci";

		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */

		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */

		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */

		reg-names = "pads", "afi", "cs";

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */

			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */

		interrupt-names = "intr", "msi";



		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;



		bus-range = <0x00 0xff>;

		#address-cells = <3>;

		#size-cells = <2>;



		ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */

			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */

			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */

			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */

			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */



		clocks = <&tegra_car TEGRA210_CLK_PCIE>,

			 <&tegra_car TEGRA210_CLK_AFI>,

			 <&tegra_car TEGRA210_CLK_PLL_E>,

			 <&tegra_car TEGRA210_CLK_CML0>;

		clock-names = "pex", "afi", "pll_e", "cml";

		resets = <&tegra_car 70>,

			 <&tegra_car 72>,

			 <&tegra_car 74>;

		reset-names = "pex", "afi", "pcie_x";

		status = "disabled";



		pci@1,0 {

			device_type = "pci";

			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;

			reg = <0x000800 0 0 0 0>;

			status = "disabled";



			#address-cells = <3>;

			#size-cells = <2>;

			ranges;



			nvidia,num-lanes = <4>;

		};



		pci@2,0 {

			device_type = "pci";

			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;

			reg = <0x001000 0 0 0 0>;

			status = "disabled";



			#address-cells = <3>;

			#size-cells = <2>;

			ranges;



			nvidia,num-lanes = <1>;

		};

	};



Board DTS:



	pcie-controller@01003000 {

		status = "okay";



		avdd-pll-uerefe-supply = <&avdd_1v05_pll>;

		hvddio-pex-supply = <&vdd_1v8>;

		dvddio-pex-supply = <&vdd_pex_1v05>;

		dvdd-pex-pll-supply = <&vdd_pex_1v05>;

		hvdd-pex-pll-e-supply = <&vdd_1v8>;

		vddio-pex-ctl-supply = <&vdd_1v8>;



		pci@1,0 {

			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,

			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,

			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,

			       <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;

			phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";

			status = "okay";

		};



		pci@2,0 {

			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;

			phy-names = "pcie-0";

			status = "okay";

		};

	};

Documentation/devicetree/bindings/pci/pci.txt

+6 −0
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@@ -18,3 +18,9 @@ driver implementation may support the following properties: 
   host bridges in the system, otherwise potentially conflicting domain numbers

   may be assigned to root buses behind different host bridges.  The domain

   number for each host bridge in the system must be unique.

- max-link-speed:

   If present this property specifies PCI gen for link capability.  Host

   drivers could add this as a strategy to avoid unnecessary operation for

   unsupported link speed, for instance, trying to do training for

   unsupported link speed, etc.  Must be '4' for gen4, '3' for gen3, '2'

   for gen2, and '1' for gen1. Any other values are invalid.