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Commit 81e7f200 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Idle unused rings on gen2/3 during init/resume 



gen2/3 platforms have a boatload of rings we're not using. On my 830
the BIOS/hw can leave some of those "active" after resume which will
prevent c3 entry. The ring is apparently considered active whenever
head != tail even if the ring is disabled.

Disable and clear all such unused ringbuffers on init/resume.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 1038392b

drivers/gpu/drm/i915/i915_gem.c

+35 −0
Original line number Diff line number Diff line
@@ -4663,11 +4663,46 @@ intel_enable_blt(struct drm_device *dev) 
	return true;

}



static void init_unused_ring(struct drm_device *dev, u32 base)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	I915_WRITE(RING_CTL(base), 0);

	I915_WRITE(RING_HEAD(base), 0);

	I915_WRITE(RING_TAIL(base), 0);

	I915_WRITE(RING_START(base), 0);

}



static void init_unused_rings(struct drm_device *dev)

{

	if (IS_I830(dev)) {

		init_unused_ring(dev, PRB1_BASE);

		init_unused_ring(dev, SRB0_BASE);

		init_unused_ring(dev, SRB1_BASE);

		init_unused_ring(dev, SRB2_BASE);

		init_unused_ring(dev, SRB3_BASE);

	} else if (IS_GEN2(dev)) {

		init_unused_ring(dev, SRB0_BASE);

		init_unused_ring(dev, SRB1_BASE);

	} else if (IS_GEN3(dev)) {

		init_unused_ring(dev, PRB1_BASE);

		init_unused_ring(dev, PRB2_BASE);

	}

}



int i915_gem_init_rings(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int ret;



	/*

	 * At least 830 can leave some of the unused rings

	 * "active" (ie. head != tail) after resume which

	 * will prevent c3 entry. Makes sure all unused rings

	 * are totally idle.

	 */

	init_unused_rings(dev);



	ret = intel_init_render_ring_buffer(dev);

	if (ret)

		return ret;

drivers/gpu/drm/i915/i915_reg.h

+7 −0
Original line number Diff line number Diff line
@@ -1026,6 +1026,13 @@ enum punit_power_well { 
#define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */

#define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */

#define PGTBL_ER	0x02024

#define PRB0_BASE (0x2030-0x30)

#define PRB1_BASE (0x2040-0x30) /* 830,gen3 */

#define PRB2_BASE (0x2050-0x30) /* gen3 */

#define SRB0_BASE (0x2100-0x30) /* gen2 */

#define SRB1_BASE (0x2110-0x30) /* gen2 */

#define SRB2_BASE (0x2120-0x30) /* 830 */

#define SRB3_BASE (0x2130-0x30) /* 830 */

#define RENDER_RING_BASE	0x02000

#define BSD_RING_BASE		0x04000

#define GEN6_BSD_RING_BASE	0x12000