Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7eebcde6 authored by Arun Siluvery's avatar Arun Siluvery Committed by Daniel Vetter
Browse files

drm/i915/gen8: Move GEN7_GT_MODE WA to common init fn 



Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 48404636

drivers/gpu/drm/i915/intel_ringbuffer.c

+12 −24
Original line number Diff line number Diff line
@@ -827,6 +827,18 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring) 
	/* Wa4x4STCOptimizationDisable:bdw,chv */

	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);



	/*

	 * BSpec recommends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.

	 *

	 * Note that PS/WM thread counts depend on the WIZ hashing

	 * disable bit, which we don't touch here, but it's good

	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).

	 */

	WA_SET_FIELD_MASKED(GEN7_GT_MODE,

			    GEN6_WIZ_HASHING_MASK,

			    GEN6_WIZ_HASHING_16x4);



	return 0;

}
@@ -864,18 +876,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) 
			  /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */

			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));



	/*

	 * BSpec recommends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.

	 *

	 * Note that PS/WM thread counts depend on the WIZ hashing

	 * disable bit, which we don't touch here, but it's good

	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).

	 */

	WA_SET_FIELD_MASKED(GEN7_GT_MODE,

			    GEN6_WIZ_HASHING_MASK,

			    GEN6_WIZ_HASHING_16x4);



	return 0;

}
@@ -905,18 +905,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) 
	/* Improve HiZ throughput on CHV. */

	WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);



	/*

	 * BSpec recommends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.

	 *

	 * Note that PS/WM thread counts depend on the WIZ hashing

	 * disable bit, which we don't touch here, but it's good

	 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).

	 */

	WA_SET_FIELD_MASKED(GEN7_GT_MODE,

			    GEN6_WIZ_HASHING_MASK,

			    GEN6_WIZ_HASHING_16x4);



	return 0;

}