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Commit 48404636 authored by Arun Siluvery's avatar Arun Siluvery Committed by Daniel Vetter
Browse files

drm/i915/gen8: Move Wa4x4STCOptimizationDisable to common init fn 



Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 6def8fdd

drivers/gpu/drm/i915/intel_ringbuffer.c

+3 −8
Original line number Diff line number Diff line
@@ -824,6 +824,9 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring) 
	 */

	WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);



	/* Wa4x4STCOptimizationDisable:bdw,chv */

	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);



	return 0;

}
@@ -861,10 +864,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) 
			  /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */

			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));



	/* Wa4x4STCOptimizationDisable:bdw */

	WA_SET_BIT_MASKED(CACHE_MODE_1,

			  GEN8_4x4_STC_OPTIMIZATION_DISABLE);



	/*

	 * BSpec recommends 8x4 when MSAA is used,

	 * however in practice 16x4 seems fastest.
@@ -903,10 +902,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) 
			  HDC_FORCE_NON_COHERENT |

			  HDC_DONOT_FETCH_MEM_WHEN_MASKED);



	/* Wa4x4STCOptimizationDisable:chv */

	WA_SET_BIT_MASKED(CACHE_MODE_1,

			  GEN8_4x4_STC_OPTIMIZATION_DISABLE);



	/* Improve HiZ throughput on CHV. */

	WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);