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Commit 6def8fdd authored by Arun Siluvery's avatar Arun Siluvery Committed by Daniel Vetter
Browse files

drm/i915/gen8: Move HiZ RAW stall optimization disable WA to common init fn 



Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent d0581194

drivers/gpu/drm/i915/intel_ringbuffer.c

+10 −15
Original line number Diff line number Diff line
@@ -814,6 +814,16 @@ static int gen8_init_workarounds(struct intel_engine_cs *ring) 
	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,

			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);



	/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:

	 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping

	 *  polygons in the same 8x4 pixel/sample area to be processed without

	 *  stalling waiting for the earlier ones to write to Hierarchical Z

	 *  buffer."

	 *

	 * This optimization is off by default for BDW and CHV; turn it on.

	 */

	WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);



	return 0;

}
@@ -851,16 +861,6 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) 
			  /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */

			  (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));



	/* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:

	 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping

	 *  polygons in the same 8x4 pixel/sample area to be processed without

	 *  stalling waiting for the earlier ones to write to Hierarchical Z

	 *  buffer."

	 *

	 * This optimization is off by default for Broadwell; turn it on.

	 */

	WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);



	/* Wa4x4STCOptimizationDisable:bdw */

	WA_SET_BIT_MASKED(CACHE_MODE_1,

			  GEN8_4x4_STC_OPTIMIZATION_DISABLE);
@@ -903,11 +903,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) 
			  HDC_FORCE_NON_COHERENT |

			  HDC_DONOT_FETCH_MEM_WHEN_MASKED);



	/* According to the CACHE_MODE_0 default value documentation, some

	 * CHV platforms disable this optimization by default.  Turn it on.

	 */

	WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);



	/* Wa4x4STCOptimizationDisable:chv */

	WA_SET_BIT_MASKED(CACHE_MODE_1,

			  GEN8_4x4_STC_OPTIMIZATION_DISABLE);