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Commit 7ee16f7b authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata
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drm/msm/dsi-staging: selectively enable DSI clk gating 



Enable DSI PHY and pixel clock gating selectively on DSI PHY 0
in split DSI usecase.

Change-Id: I3fc58f8912431c459f0b2f9f8fdb41f11a55b326
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent 37033e1b
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