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Commit 6a4ccd9a authored by Beniamino Galvani's avatar Beniamino Galvani Committed by Carlo Caione
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ARM: meson: enable L2 cache 



This enables the L2 cache controller available in Amlogic SoCs.

Signed-off-by: default avatarBeniamino Galvani <b.galvani@gmail.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarCarlo Caione <carlo@caione.org>
parent a25a6772
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