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Commit 691038ba authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Ralf Baechle
Browse files

MIPS: Add missing bits for Config registers 



Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Acked-by: default avatarDavid Daney <david.daney@cavium.com>
Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6128/
parent 795038a6

arch/mips/include/asm/mipsregs.h

+38 −2
Original line number Original line Diff line number Diff line
@@ -573,7 +573,9 @@ 
#define MIPS_CONF1_IA		(_ULCAST_(7) << 16)

#define MIPS_CONF1_IA		(_ULCAST_(7) << 16)

#define MIPS_CONF1_IL		(_ULCAST_(7) << 19)

#define MIPS_CONF1_IL		(_ULCAST_(7) << 19)

#define MIPS_CONF1_IS		(_ULCAST_(7) << 22)

#define MIPS_CONF1_IS		(_ULCAST_(7) << 22)

#define MIPS_CONF1_TLBS		(_ULCAST_(63)<< 25)

#define MIPS_CONF1_TLBS_SHIFT   (25)

#define MIPS_CONF1_TLBS_SIZE    (6)

#define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)





#define MIPS_CONF2_SA		(_ULCAST_(15)<<	 0)

#define MIPS_CONF2_SA		(_ULCAST_(15)<<	 0)

#define MIPS_CONF2_SL		(_ULCAST_(15)<<	 4)

#define MIPS_CONF2_SL		(_ULCAST_(15)<<	 4)
@@ -587,21 +589,53 @@ 
#define MIPS_CONF3_TL		(_ULCAST_(1) <<	 0)

#define MIPS_CONF3_TL		(_ULCAST_(1) <<	 0)

#define MIPS_CONF3_SM		(_ULCAST_(1) <<	 1)

#define MIPS_CONF3_SM		(_ULCAST_(1) <<	 1)

#define MIPS_CONF3_MT		(_ULCAST_(1) <<	 2)

#define MIPS_CONF3_MT		(_ULCAST_(1) <<	 2)

#define MIPS_CONF3_CDMM		(_ULCAST_(1) <<	 3)

#define MIPS_CONF3_SP		(_ULCAST_(1) <<	 4)

#define MIPS_CONF3_SP		(_ULCAST_(1) <<	 4)

#define MIPS_CONF3_VINT		(_ULCAST_(1) <<	 5)

#define MIPS_CONF3_VINT		(_ULCAST_(1) <<	 5)

#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<	 6)

#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<	 6)

#define MIPS_CONF3_LPA		(_ULCAST_(1) <<	 7)

#define MIPS_CONF3_LPA		(_ULCAST_(1) <<	 7)

#define MIPS_CONF3_ITL		(_ULCAST_(1) <<	 8)

#define MIPS_CONF3_CTXTC	(_ULCAST_(1) <<	 9)

#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)

#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)

#define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)

#define MIPS_CONF3_DSP2P	(_ULCAST_(1) << 11)

#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)

#define MIPS_CONF3_RXI		(_ULCAST_(1) << 12)

#define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)

#define MIPS_CONF3_ULRI		(_ULCAST_(1) << 13)

#define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)

#define MIPS_CONF3_ISA		(_ULCAST_(3) << 14)

#define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)

#define MIPS_CONF3_ISA_OE	(_ULCAST_(1) << 16)

#define MIPS_CONF3_MCU		(_ULCAST_(1) << 17)

#define MIPS_CONF3_MMAR		(_ULCAST_(7) << 18)

#define MIPS_CONF3_IPLW		(_ULCAST_(3) << 21)

#define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)

#define MIPS_CONF3_VZ		(_ULCAST_(1) << 23)



#define MIPS_CONF3_PW		(_ULCAST_(1) << 24)

#define MIPS_CONF3_SC		(_ULCAST_(1) << 25)

#define MIPS_CONF3_BI		(_ULCAST_(1) << 26)

#define MIPS_CONF3_BP		(_ULCAST_(1) << 27)

#define MIPS_CONF3_MSA		(_ULCAST_(1) << 28)

#define MIPS_CONF3_CMGCR	(_ULCAST_(1) << 29)

#define MIPS_CONF3_BPG		(_ULCAST_(1) << 30)



#define MIPS_CONF4_MMUSIZEEXT_SHIFT	(0)

#define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)

#define MIPS_CONF4_MMUSIZEEXT	(_ULCAST_(255) << 0)

#define MIPS_CONF4_FTLBSETS_SHIFT	(0)

#define MIPS_CONF4_FTLBSETS_SHIFT	(0)

#define MIPS_CONF4_FTLBSETS	(_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)

#define MIPS_CONF4_FTLBWAYS_SHIFT	(4)

#define MIPS_CONF4_FTLBWAYS	(_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)

#define MIPS_CONF4_FTLBPAGESIZE_SHIFT	(8)

/* bits 10:8 in FTLB-only configurations */

#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)

/* bits 12:8 in VTLB-FTLB only configurations */

#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)

#define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)

#define MIPS_CONF4_MMUEXTDEF	(_ULCAST_(3) << 14)

#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)

#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)

#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT	(_ULCAST_(2) << 14)

#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT	(_ULCAST_(3) << 14)

#define MIPS_CONF4_KSCREXIST	(_ULCAST_(255) << 16)

#define MIPS_CONF4_VTLBSIZEEXT_SHIFT	(24)

#define MIPS_CONF4_VTLBSIZEEXT	(_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)

#define MIPS_CONF4_AE		(_ULCAST_(1) << 28)

#define MIPS_CONF4_IE		(_ULCAST_(3) << 29)

#define MIPS_CONF4_TLBINV	(_ULCAST_(2) << 29)





#define MIPS_CONF5_NF		(_ULCAST_(1) << 0)

#define MIPS_CONF5_NF		(_ULCAST_(1) << 0)

#define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)

#define MIPS_CONF5_UFR		(_ULCAST_(1) << 2)
@@ -616,6 +650,8 @@ 




#define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)

#define MIPS_CONF7_RPS		(_ULCAST_(1) << 2)





/*  EntryHI bit definition */

#define MIPS_ENTRYHI_EHINV	(_ULCAST_(1) << 10)





/*

/*

 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.

 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.