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Commit 58641745 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Disable PCIe l0s low power mode for QCS405"

parents 4116a143 762ad017

Documentation/devicetree/bindings/pci/msm_pcie.txt

+1 −0
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ Optional Properties: 
  - reset-names: reset signal name strings sorted in the same order as the resets

    property.

  - clock-output-names: name of the outgoing clock signal from the PHY PLL.

  - qcom,keep-powerdown-phy: If present, power down phy in probe to avoid leakage.



=================

Root Complex node

arch/arm64/boot/dts/qcom/qcs405-pcie.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -83,6 +83,8 @@ 
		qcom,phy-status-bit = <0>;

		qcom,phy-power-down-offset = <0x98>;

		qcom,boot-option = <0x1>;

		qcom,keep-powerdown-phy;

		qcom,no-l0s-supported;



		linux,pci-domain = <0>;

drivers/pci/host/pci-msm.c

+18 −0
Original line number Diff line number Diff line
@@ -733,6 +733,7 @@ struct msm_pcie_dev_t { 
	bool				use_19p2mhz_aux_clk;

	bool				use_pinctrl;

	bool enable_l1ss_timeout;

	bool				keep_powerdown_phy;

	struct pinctrl			*pinctrl;

	struct pinctrl_state		*pins_default;

	struct pinctrl_state		*pins_sleep;
@@ -3194,6 +3195,11 @@ static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev) 
		regulator_disable(dev->gdsc);

	}



	/* Clear power down bit to enable PHY */

	if (dev->keep_powerdown_phy && dev->phy_power_down_offset)

		msm_pcie_write_mask(dev->phy + dev->phy_power_down_offset, 0,

									BIT(4));



	for (i = 0; i < MSM_PCIE_MAX_RESET; i++) {

		reset_info = &dev->reset[i];

		if (reset_info->hdl) {
@@ -5914,6 +5920,18 @@ static int msm_pcie_probe(struct platform_device *pdev) 
		PCIE_DBG(&msm_pcie_dev[rc_idx],

			"PCIe:RC%d didn't register pipeclock source\n", rc_idx);



	msm_pcie_dev[rc_idx].keep_powerdown_phy =

		of_property_read_bool((&pdev->dev)->of_node,

				"qcom,keep-powerdown-phy");

	/* Power down PHY to avoid leakage at 1.8V LDO */

	if (msm_pcie_dev[rc_idx].keep_powerdown_phy &&

				msm_pcie_dev[rc_idx].phy_power_down_offset) {

		msm_pcie_clk_init(&msm_pcie_dev[rc_idx]);

		msm_pcie_write_reg(msm_pcie_dev[rc_idx].phy,

				msm_pcie_dev[rc_idx].phy_power_down_offset, 0);

		msm_pcie_clk_deinit(&msm_pcie_dev[rc_idx]);

	}



	if (msm_pcie_dev[rc_idx].boot_option &

			MSM_PCIE_NO_PROBE_ENUMERATION) {

		PCIE_DBG(&msm_pcie_dev[rc_idx],