Loading arch/arm64/boot/dts/qcom/sa8155-vm.dtsi +17 −2 Original line number Diff line number Diff line Loading @@ -38,8 +38,8 @@ <0x17080000 0xE000>; reg-names = "lpa_if", "lpass_tcsr"; interrupts = <GIC_SPI 267 0>; bit-clock-hz = <20000000>; interrupt-interval-ms = <10>; number-of-rate-detectors = <2>; rate-detector-interfaces = <0 1>; sdr0: qcom,hs0_i2s { compatible = "qcom,hsi2s-interface"; Loading @@ -51,6 +51,11 @@ pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep &hs1_i2s_data1_sleep>; bit-clock-hz = <12288000>; data-buffer-ms = <10>; bit-depth = <32>; spkr-channel-count = <2>; mic-channel-count = <2>; }; sdr1: qcom,hs1_i2s { Loading @@ -63,6 +68,11 @@ pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep &hs2_i2s_data1_sleep>; bit-clock-hz = <12288000>; data-buffer-ms = <10>; bit-depth = <32>; spkr-channel-count = <2>; mic-channel-count = <2>; }; sdr2: qcom,hs2_i2s { Loading @@ -75,6 +85,11 @@ pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep &hs3_i2s_data1_sleep>; bit-clock-hz = <12288000>; data-buffer-ms = <10>; bit-depth = <32>; spkr-channel-count = <2>; mic-channel-count = <2>; }; }; Loading Loading
arch/arm64/boot/dts/qcom/sa8155-vm.dtsi +17 −2 Original line number Diff line number Diff line Loading @@ -38,8 +38,8 @@ <0x17080000 0xE000>; reg-names = "lpa_if", "lpass_tcsr"; interrupts = <GIC_SPI 267 0>; bit-clock-hz = <20000000>; interrupt-interval-ms = <10>; number-of-rate-detectors = <2>; rate-detector-interfaces = <0 1>; sdr0: qcom,hs0_i2s { compatible = "qcom,hsi2s-interface"; Loading @@ -51,6 +51,11 @@ pinctrl-1 = <&hs1_i2s_mclk_sleep &hs1_i2s_sck_sleep &hs1_i2s_ws_sleep &hs1_i2s_data0_sleep &hs1_i2s_data1_sleep>; bit-clock-hz = <12288000>; data-buffer-ms = <10>; bit-depth = <32>; spkr-channel-count = <2>; mic-channel-count = <2>; }; sdr1: qcom,hs1_i2s { Loading @@ -63,6 +68,11 @@ pinctrl-1 = <&hs2_i2s_mclk_sleep &hs2_i2s_sck_sleep &hs2_i2s_ws_sleep &hs2_i2s_data0_sleep &hs2_i2s_data1_sleep>; bit-clock-hz = <12288000>; data-buffer-ms = <10>; bit-depth = <32>; spkr-channel-count = <2>; mic-channel-count = <2>; }; sdr2: qcom,hs2_i2s { Loading @@ -75,6 +85,11 @@ pinctrl-1 = <&hs3_i2s_mclk_sleep &hs3_i2s_sck_sleep &hs3_i2s_ws_sleep &hs3_i2s_data0_sleep &hs3_i2s_data1_sleep>; bit-clock-hz = <12288000>; data-buffer-ms = <10>; bit-depth = <32>; spkr-channel-count = <2>; mic-channel-count = <2>; }; }; Loading