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Commit 4e1f224d authored by Jeevan Shriram's avatar Jeevan Shriram
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ARM: dts: msm: Add L1 cache definitions to sdmshrike target 



Ad L1 I/D cache nodes and cpu dump nodes for sdmshrike target.

Change-Id: I0381321dc83983812b1cb8f4084c23eb482a653e
Signed-off-by: default avatarJeevan Shriram <jshriram@codeaurora.org>
parent 8c3a7f09
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