Commit 4db518e4 authored May 11, 2018 by Chris Wilson

drm/i915/execlists: Relax CSB force-mmio for VT-d

The original switch to use CSB from the HWSP was plagued by the effect
of read ordering on VT-d; we would read the WRITE pointer from the HWSP
before it had completed writing the CSB contents. The mystery comes down
to the lack of rmb() for correct ordering with respect to the writes
from HW, and with that resolved we can remove the VT-d special casing.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180511121147.31915-3-chris@chris-wilson.co.uk

Tested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

parent b1705f72

drivers/gpu/drm/i915/intel_engine_cs.c

+0 −8

Original line number	Diff line number	Diff line
		@@ -458,14 +458,6 @@ static void intel_engine_init_batch_pool(struct intel_engine_cs *engine)

		static bool csb_force_mmio(struct drm_i915_private *i915)
		{
		/*
		* IOMMU adds unpredictable latency causing the CSB write (from the
		* GPU into the HWSP) to only be visible some time after the interrupt
		* (missed breadcrumb syndrome).
		*/
		if (intel_vtd_active())
		return true;

		/* Older GVT emulation depends upon intercepting CSB mmio */
		if (intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915))
		return true;