Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b1705f72 authored by Jani Nikula's avatar Jani Nikula
Browse files

Merge tag 'gvt-next-2018-05-14' of https://github.com/intel/gvt-linux into drm-intel-next-queued 



- Improve the emulation of virtual non-priv register. (Yan)
- Reverse the hack of host of preeption of GVT-g. (Weinan)
- Improve untracked warning message.(Changbin)

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ebae7cf1-6550-bb44-74a2-d3a014051804@intel.com
parents 0c79f9cb 41e403d0

drivers/gpu/drm/i915/gvt/cmd_parser.c

+21 −5
Original line number Diff line number Diff line
@@ -813,15 +813,31 @@ static inline bool is_force_nonpriv_mmio(unsigned int offset) 
}



static int force_nonpriv_reg_handler(struct parser_exec_state *s,

				     unsigned int offset, unsigned int index)

		unsigned int offset, unsigned int index, char *cmd)

{

	struct intel_gvt *gvt = s->vgpu->gvt;

	unsigned int data = cmd_val(s, index + 1);

	unsigned int data;

	u32 ring_base;

	u32 nopid;

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data)) {

	if (!strcmp(cmd, "lri"))

		data = cmd_val(s, index + 1);

	else {

		gvt_err("Unexpected forcenonpriv 0x%x write from cmd %s\n",

			offset, cmd);

		return -EINVAL;

	}



	ring_base = dev_priv->engine[s->ring_id]->mmio_base;

	nopid = i915_mmio_reg_offset(RING_NOPID(ring_base));



	if (!intel_gvt_in_force_nonpriv_whitelist(gvt, data) &&

			data != nopid) {

		gvt_err("Unexpected forcenonpriv 0x%x LRI write, value=0x%x\n",

			offset, data);

		return -EPERM;

		patch_value(s, cmd_ptr(s, index), nopid);

		return 0;

	}

	return 0;

}
@@ -869,7 +885,7 @@ static int cmd_reg_handler(struct parser_exec_state *s, 
		return -EINVAL;



	if (is_force_nonpriv_mmio(offset) &&

		force_nonpriv_reg_handler(s, offset, index))

		force_nonpriv_reg_handler(s, offset, index, cmd))

		return -EPERM;



	if (offset == i915_mmio_reg_offset(DERRMR) ||

drivers/gpu/drm/i915/gvt/gvt.h

+0 −1
Original line number Diff line number Diff line
@@ -99,7 +99,6 @@ struct intel_vgpu_fence { 
struct intel_vgpu_mmio {

	void *vreg;

	void *sreg;

	bool disable_warn_untrack;

};



#define INTEL_GVT_MAX_BAR_NUM 4

drivers/gpu/drm/i915/gvt/handlers.c

+18 −17
Original line number Diff line number Diff line
@@ -191,6 +191,8 @@ static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 
	unsigned int max_fence = vgpu_fence_sz(vgpu);



	if (fence_num >= max_fence) {

		gvt_vgpu_err("access oob fence reg %d/%d\n",

			     fence_num, max_fence);



		/* When guest access oob fence regs without access

		 * pv_info first, we treat guest not supporting GVT,
@@ -200,11 +202,6 @@ static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu, 
			enter_failsafe_mode(vgpu,

					GVT_FAILSAFE_UNSUPPORTED_GUEST);



		if (!vgpu->mmio.disable_warn_untrack) {

			gvt_vgpu_err("found oob fence register access\n");

			gvt_vgpu_err("total fence %d, access fence %d\n",

				     max_fence, fence_num);

		}

		memset(p_data, 0, bytes);

		return -EINVAL;

	}
@@ -477,22 +474,28 @@ static int force_nonpriv_write(struct intel_vgpu *vgpu, 
	unsigned int offset, void *p_data, unsigned int bytes)

{

	u32 reg_nonpriv = *(u32 *)p_data;

	int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);

	u32 ring_base;

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;

	int ret = -EINVAL;



	if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {

		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",

			vgpu->id, offset, bytes);

	if ((bytes != 4) || ((offset & (bytes - 1)) != 0) || ring_id < 0) {

		gvt_err("vgpu(%d) ring %d Invalid FORCE_NONPRIV offset %x(%dB)\n",

			vgpu->id, ring_id, offset, bytes);

		return ret;

	}



	if (in_whitelist(reg_nonpriv)) {

	ring_base = dev_priv->engine[ring_id]->mmio_base;



	if (in_whitelist(reg_nonpriv) ||

		reg_nonpriv == i915_mmio_reg_offset(RING_NOPID(ring_base))) {

		ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,

			bytes);

	} else {

		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",

			vgpu->id, reg_nonpriv);

	}

	return ret;

	} else

		gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",

			vgpu->id, reg_nonpriv, offset);



	return 0;

}



static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
@@ -3092,9 +3095,7 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, 
	 */

	mmio_info = find_mmio_info(gvt, offset);

	if (!mmio_info) {

		if (!vgpu->mmio.disable_warn_untrack)

			gvt_vgpu_err("untracked MMIO %08x len %d\n",

				     offset, bytes);

		gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);

		goto default_rw;

	}

drivers/gpu/drm/i915/gvt/mmio.c

+0 −2
Original line number Diff line number Diff line
@@ -244,8 +244,6 @@ void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr) 


		/* set the bit 0:2(Core C-State ) to C0 */

		vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;



		vgpu->mmio.disable_warn_untrack = false;

	} else {

#define GVT_GEN8_MMIO_RESET_OFFSET		(0x44200)

		/* only reset the engine related, so starting with 0x44200

drivers/gpu/drm/i915/gvt/scheduler.c

+0 −3
Original line number Diff line number Diff line
@@ -1156,9 +1156,6 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu) 
	if (IS_ERR(s->shadow_ctx))

		return PTR_ERR(s->shadow_ctx);



	if (HAS_LOGICAL_RING_PREEMPTION(vgpu->gvt->dev_priv))

		s->shadow_ctx->sched.priority = INT_MAX;



	bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);



	s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",