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Commit 4c601e0d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v4.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control fixes from Linus Walleij:
 "Nothing special at all, just three SoC-specific driver fixes:

   - Fix routing problems in pistachio (Imagination) and sunxi
     (AllWinner)

   - Fix an interrupt problem in the Cherryview (Intel)"

* tag 'pinctrl-v4.8-3' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33
  pinctrl: cherryview: Do not mask all interrupts in probe
  pinctrl: pistachio: fix mfio pll_lock pinmux
parents bc4dee5a 486095fa

drivers/pinctrl/intel/pinctrl-cherryview.c

+2 −3
Original line number Diff line number Diff line
@@ -1539,12 +1539,11 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) 
		offset += range->npins;

	}



	/* Mask and clear all interrupts */

	chv_writel(0, pctrl->regs + CHV_INTMASK);

	/* Clear all interrupts */

	chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);



	ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,

				   handle_simple_irq, IRQ_TYPE_NONE);

				   handle_bad_irq, IRQ_TYPE_NONE);

	if (ret) {

		dev_err(pctrl->dev, "failed to add IRQ chip\n");

		goto fail;

drivers/pinctrl/pinctrl-pistachio.c

+6 −6
Original line number Diff line number Diff line
@@ -809,17 +809,17 @@ static const struct pistachio_pin_group pistachio_groups[] = { 
			   PADS_FUNCTION_SELECT2, 12, 0x3),

	MFIO_MUX_PIN_GROUP(83, MIPS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,

			   PADS_FUNCTION_SELECT2, 14, 0x3),

	MFIO_MUX_PIN_GROUP(84, SYS_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,

	MFIO_MUX_PIN_GROUP(84, AUDIO_PLL_LOCK, MIPS_TRACE_DATA, USB_DEBUG,

			   PADS_FUNCTION_SELECT2, 16, 0x3),

	MFIO_MUX_PIN_GROUP(85, WIFI_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,

	MFIO_MUX_PIN_GROUP(85, RPU_V_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,

			   PADS_FUNCTION_SELECT2, 18, 0x3),

	MFIO_MUX_PIN_GROUP(86, BT_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,

	MFIO_MUX_PIN_GROUP(86, RPU_L_PLL_LOCK, MIPS_TRACE_DATA, SDHOST_DEBUG,

			   PADS_FUNCTION_SELECT2, 20, 0x3),

	MFIO_MUX_PIN_GROUP(87, RPU_V_PLL_LOCK, DREQ2, SOCIF_DEBUG,

	MFIO_MUX_PIN_GROUP(87, SYS_PLL_LOCK, DREQ2, SOCIF_DEBUG,

			   PADS_FUNCTION_SELECT2, 22, 0x3),

	MFIO_MUX_PIN_GROUP(88, RPU_L_PLL_LOCK, DREQ3, SOCIF_DEBUG,

	MFIO_MUX_PIN_GROUP(88, WIFI_PLL_LOCK, DREQ3, SOCIF_DEBUG,

			   PADS_FUNCTION_SELECT2, 24, 0x3),

	MFIO_MUX_PIN_GROUP(89, AUDIO_PLL_LOCK, DREQ4, DREQ5,

	MFIO_MUX_PIN_GROUP(89, BT_PLL_LOCK, DREQ4, DREQ5,

			   PADS_FUNCTION_SELECT2, 26, 0x3),

	PIN_GROUP(TCK, "tck"),

	PIN_GROUP(TRSTN, "trstn"),

drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c

+2 −2
Original line number Diff line number Diff line
@@ -485,12 +485,12 @@ static const struct sunxi_desc_pin sun8i_a23_pins[] = { 
	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */

		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)),	/* PG_EINT8 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */

		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)),	/* PG_EINT9 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c

+2 −2
Original line number Diff line number Diff line
@@ -407,12 +407,12 @@ static const struct sunxi_desc_pin sun8i_a33_pins[] = { 
	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */

		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)),	/* PG_EINT8 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */

		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)),	/* PG_EINT9 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),

		  SUNXI_FUNCTION(0x0, "gpio_in"),