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Commit 486095fa authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Linus Walleij
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pinctrl: sunxi: fix uart1 CTS/RTS pins at PG on A23/A33 



PG8, PG9 is said to be the CTS/RTS pins for UART1 according to the A23/33
datasheets. However, the function is wrongly named "uart2" in the pinctrl
driver. This patch fixes this by modifying them to be named "uart1".

Cc: stable@vger.kernel.org
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.xyz>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent bcb48cca

drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c

+2 −2
Original line number Diff line number Diff line
@@ -485,12 +485,12 @@ static const struct sunxi_desc_pin sun8i_a23_pins[] = { 
	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */

		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 8)),	/* PG_EINT8 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */

		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x4, 2, 9)),	/* PG_EINT9 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c

+2 −2
Original line number Diff line number Diff line
@@ -407,12 +407,12 @@ static const struct sunxi_desc_pin sun8i_a33_pins[] = { 
	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */

		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)),	/* PG_EINT8 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),

		  SUNXI_FUNCTION(0x0, "gpio_in"),

		  SUNXI_FUNCTION(0x1, "gpio_out"),

		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */

		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */

		  SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)),	/* PG_EINT9 */

	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),

		  SUNXI_FUNCTION(0x0, "gpio_in"),