Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Skip to content
Commit 4ae8bdf7 authored by Tingwei Zhang's avatar Tingwei Zhang
Browse files

coresight: tmc: Clear CacheCtrlBit2 and CacheCtrlBit3 



TMC ETR should be set to non-cachable and bufferable.
CacheCtrlBit2 and CacheCtrlBit3 should be set 0.

Change-Id: I4d45fa1dccb4c4a33b725e5ecac80679902451a7
Signed-off-by: default avatarTingwei Zhang <tingwei@codeaurora.org>
parent 5003c472
Hide whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment