defconfig: sdm855: Enable DCC on core0

Enable kernel config HVC_DCC_SERIALIZE_SMP flag, to schedule
DCC on core 0 only.

Some debuggers, such as Trace32 from Lauterbach GmbH, do not handle
reads/writes from/to DCC on secondary cores.  Each core has its
own DCC device registers, so when a core reads or writes from/to DCC,
it only accesses its own DCC device.  Since kernel code can run on
any core, every time the kernel wants to write to the console, it
might write to a different DCC.

Selecting this option will enable code that serializes all console
input and output to core 0.  The DCC driver will create input and
output FIFOs that all cores will use.  Reads and writes from/to DCC
are handled by a workqueue that runs only core 0.

Change-Id: Ia850e5bfca80b537b3f71584d526c9711ea74280
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>