Merge "ARM: dts: msm: Add BLSP SE dt node for SPI on sdxprairie" (469e6b1d) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm64/boot/dts/qcom/sdxprairie-blsp.dtsi

+104 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,10 @@
		i2c5 = &i2c_5;
		i2c6 = &i2c_6;
		i2c7 = &i2c_7;
		spi1 = &spi_1;
		spi2 = &spi_2;
		spi3 = &spi_3;
		spi4 = &spi_4;
		};
		};

		@@ -193,4 +197,104 @@
		status = "disabled";
		};

		spi_1: spi@835000 { /* BLSP1 QUP1: GPIO: 80,81,82,83 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x835000 0x600>,
		<0x804000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 31 0>, <0 58 0>;
		spi-max-frequency = <50000000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <8>;
		qcom,bam-producer-pipe-index = <9>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_1_active>;
		pinctrl-1 = <&spi_1_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
		<&clock_gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
		status = "disabled";
		};

		spi_2: spi@836000 { /* BLSP1 QUP2: GPIO: 4,5,6,7 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x836000 0x600>,
		<0x804000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 32 0>, <0 58 0>;
		spi-max-frequency = <50000000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <10>;
		qcom,bam-producer-pipe-index = <11>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_2_active>;
		pinctrl-1 = <&spi_2_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
		<&clock_gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
		status = "disabled";
		};

		spi_3: spi@837000 { /* BLSP1 QUP3: GPIO: 8,9,10,11 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x837000 0x600>,
		<0x804000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 33 0>, <0 58 0>;
		spi-max-frequency = <50000000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <12>;
		qcom,bam-producer-pipe-index = <13>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_3_active>;
		pinctrl-1 = <&spi_3_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
		<&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
		status = "disabled";
		};

		spi_4: spi@838000 { /* BLSP1 QUP4: GPIO: 16,17,18,19 */
		compatible = "qcom,spi-qup-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "spi_physical", "spi_bam_physical";
		reg = <0x838000 0x600>,
		<0x804000 0x23000>;
		interrupt-names = "spi_irq", "spi_bam_irq";
		interrupts = <0 34 0>, <0 58 0>;
		spi-max-frequency = <50000000>;
		qcom,use-bam;
		qcom,ver-reg-exists;
		qcom,bam-consumer-pipe-index = <14>;
		qcom,bam-producer-pipe-index = <15>;
		qcom,master-id = <86>;
		qcom,use-pinctrl;
		pinctrl-names = "spi_default", "spi_sleep";
		pinctrl-0 = <&spi_4_active>;
		pinctrl-1 = <&spi_4_sleep>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
		<&clock_gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
		status = "disabled";
		};

		};

arch/arm64/boot/dts/qcom/sdxprairie-pinctrl.dtsi

+129 −0

Original line number	Diff line number	Diff line
		@@ -244,5 +244,134 @@
		};
		};

		/SPI Configuration/
		spi_1 {
		spi_1_active: spi_1_active {
		mux {
		pins = "gpio80", "gpio81",
		"gpio82", "gpio83";
		function = "blsp_spi1";
		};

		config {
		pins = "gpio80", "gpio81",
		"gpio82", "gpio83";
		drive-strength = <6>;
		bias-disable;
		};
		};

		spi_1_sleep: spi_1_sleep {
		mux {
		pins = "gpio80", "gpio81",
		"gpio82", "gpio83";
		function = "blsp_spi1";
		};

		config {
		pins = "gpio80", "gpio81",
		"gpio82", "gpio83";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		spi_2 {
		spi_2_active: spi_2_active {
		mux {
		pins = "gpio4", "gpio5",
		"gpio6", "gpio7";
		function = "blsp_spi2";
		};

		config {
		pins = "gpio4", "gpio5",
		"gpio6", "gpio7";
		drive-strength = <6>;
		bias-disable;
		};
		};

		spi_2_sleep: spi_2_sleep {
		mux {
		pins = "gpio4", "gpio5",
		"gpio6", "gpio7";
		function = "blsp_spi2";
		};

		config {
		pins = "gpio4", "gpio5",
		"gpio6", "gpio7";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		spi_3 {
		spi_3_active: spi_3_active {
		mux {
		pins = "gpio8", "gpio9",
		"gpio10", "gpio11";
		function = "blsp_spi3";
		};

		config {
		pins = "gpio8", "gpio9",
		"gpio10", "gpio11";
		drive-strength = <6>;
		bias-disable;
		};
		};

		spi_3_sleep: spi_3_sleep {
		mux {
		pins = "gpio8", "gpio9",
		"gpio10", "gpio11";
		function = "blsp_spi3";
		};

		config {
		pins = "gpio8", "gpio9",
		"gpio10", "gpio11";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		spi_4 {
		spi_4_active: spi_4_active {
		mux {
		pins = "gpio16", "gpio17",
		"gpio18", "gpio19";
		function = "blsp_spi4";
		};

		config {
		pins = "gpio16", "gpio17",
		"gpio18", "gpio19";
		drive-strength = <6>;
		bias-disable;
		};
		};

		spi_4_sleep: spi_4_sleep {
		mux {
		pins = "gpio16", "gpio17",
		"gpio18", "gpio19";
		function = "blsp_spi4";
		};

		config {
		pins = "gpio16", "gpio17",
		"gpio18", "gpio19";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		};
		};