Commit 3fa9760d authored Aug 04, 2020 by ckosuru

Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14

* quic/dev/msm-4.14-display:
Revert "drm/msm/sde: use atomic counter for pending frame done"
Revert "drm/msm/sde: support posted frame trigger for cmd mode"
Revert "drm/msm/sde: delay reset frame by a frame for posted trigger"
Revert "drm/msm/sde: add connector property for frame trigger mode"
Revert "drm/msm/sde: avoid frame done event during autorefresh"
Revert "drm/msm/sde: trigger frame done if ctl is idle"
Revert "disp: msm: sde: use wr_ptr interrupt instead of ctl_start"
Revert "disp: msm: sde: reset ctl during wr_ptr_irq timeout"
Revert "disp: msm: sde: fix release fence signaling in error cases"
Revert "disp: msm: sde: wait for specific pp_done instead of zero"
Revert "disp: msm: sde: fix handling the missing pp-done interrupt cases"
Revert "disp: msm: sde: avoid encoder power-collapse with pending frames"
Revert "disp: msm: sde: handle another case for lost pp-done interrupt"
Revert "disp: msm: sde: signal retire fence in wr_ptr timeout"
Revert "disp: msm: sde: avoid multiple frame-done encoder events"
Revert "drm/msm/dsi-staging: update dsi clock calculations"
Revert "drm/msm/dsi-staging: update frame transfer time calculations"
Revert "disp: msm: dsi: update dsi pclk in panel mode settings"
Revert "dt-bindings: Add frame threshold property for dsi controller"
Revert "ARM: dts: msm: update frame threshold time for atoll"
Revert "drm/msm/sde: initialize sde_encoder_wait_info before usage"
Revert "drm/msm/sde: avoid frame_done event trigger for idle scenario"
Revert "drm/msm/sde: trigger single frame_done evt for vid encoder"
clk: qcom: mdss: Add check to read the gdsc status
drm/msm/sde: trigger single frame_done evt for vid encoder
drm/msm/sde: avoid frame_done event trigger for idle scenario
drm/msm/sde: initialize sde_encoder_wait_info before usage
drm/msm/dsi-staging: fix t_clk_pre in high dsi clock use case
dt-bindings: add clock_pre extend enable panel property
ARM: dts: msm: update frame threshold time for atoll
dt-bindings: Add frame threshold property for dsi controller
disp: msm: dsi: update dsi pclk in panel mode settings
drm/msm/dsi-staging: update frame transfer time calculations
drm/msm/dsi-staging: update dsi clock calculations
disp: msm: sde: avoid multiple frame-done encoder events
disp: msm: sde: signal retire fence in wr_ptr timeout
disp: msm: sde: handle another case for lost pp-done interrupt
disp: msm: sde: avoid encoder power-collapse with pending frames
disp: msm: sde: fix handling the missing pp-done interrupt cases
disp: msm: sde: wait for specific pp_done instead of zero
disp: msm: sde: fix release fence signaling in error cases
disp: msm: sde: reset ctl during wr_ptr_irq timeout
disp: msm: sde: use wr_ptr interrupt instead of ctl_start
drm/msm/sde: trigger frame done if ctl is idle
drm/msm/sde: avoid frame done event during autorefresh
drm/msm/sde: add connector property for frame trigger mode
drm/msm/sde: delay reset frame by a frame for posted trigger
drm/msm/sde: support posted frame trigger for cmd mode
drm/msm/sde: use atomic counter for pending frame done

Change-Id: I92b04e795955fe89f6e25f426325101de958102c
Signed-off-by: ckosuru <kosuru@codeaurora.org>

parents 220af9d0 1d40c0c7

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+3 −0

Original line number	Diff line number	Diff line
		@@ -265,6 +265,8 @@ Optional properties:
		0x00 = default value.
		- qcom,mdss-dsi-t-clk-pre: Specifies the byte clock cycles before mode switch.
		0x00 = default value.
		- qcom,mdss-dsi-t-clk-pre-extend: Boolean that specifies whether to enable t_clk_pre counter
		increment by 2 byteclk.
		- qcom,mdss-dsi-stream: Specifies the packet stream to be used.
		0 = stream 0 (default)
		1 = stream 1
		@@ -660,6 +662,7 @@ Example:
		qcom,lanes-per-sublink = <2>;
		qcom,mdss-dsi-t-clk-post = <0x20>;
		qcom,mdss-dsi-t-clk-pre = <0x2c>;
		qcom,mdss-dsi-t-clk-pre-extend;
		qcom,mdss-dsi-stream = <0>;
		qcom,mdss-dsi-mdp-trigger = <0>;
		qcom,mdss-dsi-dma-trigger = <0>;

arch/arm64/boot/dts/qcom/atoll-sde.dtsi

+1 −1

Original line number	Diff line number	Diff line
		/* Copyright (c) 2019, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and

drivers/clk/qcom/mdss/mdss-pll.h

+8 −2

Original line number	Diff line number	Diff line
		@@ -219,8 +219,14 @@ static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res)
		WARN(1, "gdsc_base register is not defined\n");
		return true;
		}
		if ((pll_res->target_id == MDSS_PLL_TARGET_SDM660) \|\|
		(pll_res->pll_interface_type == MDSS_DSI_PLL_12NM))
		ret = ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) &&
		(!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true;
		(!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ?
		false : true;
		else
		ret = readl_relaxed(pll_res->gdsc_base) & BIT(31) ?
		false : true;
		return ret;
		}

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h

+1 −1

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -102,6 +102,14 @@ void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,
		dsi_setup_trigger_controls(ctrl, cfg);
		dsi_split_link_setup(ctrl, cfg);

		/* Setup T_CLK_PRE extend register */
		reg_value = DSI_R32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_ENABLE);
		if (cfg->t_clk_pre_extend)
		reg_value \|= BIT(0);
		else
		reg_value &= ~BIT(0);
		DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_ENABLE, reg_value);

		/* Setup clocking timing controls */
		reg_value = ((cfg->t_clk_post & 0x3F) << 8);
		reg_value \|= (cfg->t_clk_pre & 0x3F);