Loading drivers/clk/qcom/mdss/mdss-pll.h +8 −2 Original line number Diff line number Diff line Loading @@ -219,8 +219,14 @@ static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res) WARN(1, "gdsc_base register is not defined\n"); return true; } if ((pll_res->target_id == MDSS_PLL_TARGET_SDM660) || (pll_res->pll_interface_type == MDSS_DSI_PLL_12NM)) ret = ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) && (!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true; (!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true; else ret = readl_relaxed(pll_res->gdsc_base) & BIT(31) ? false : true; return ret; } Loading Loading
drivers/clk/qcom/mdss/mdss-pll.h +8 −2 Original line number Diff line number Diff line Loading @@ -219,8 +219,14 @@ static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res) WARN(1, "gdsc_base register is not defined\n"); return true; } if ((pll_res->target_id == MDSS_PLL_TARGET_SDM660) || (pll_res->pll_interface_type == MDSS_DSI_PLL_12NM)) ret = ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) && (!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true; (!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true; else ret = readl_relaxed(pll_res->gdsc_base) & BIT(31) ? false : true; return ret; } Loading