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Commit f64a4d5f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/dsi-staging: fix t_clk_pre in high dsi clock use case"

parents 4e341a11 7bcf0d2b

Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt

+3 −0
Original line number Diff line number Diff line
@@ -265,6 +265,8 @@ Optional properties: 
					0x00 = default value.

- qcom,mdss-dsi-t-clk-pre:		Specifies the byte clock cycles before mode switch.

					0x00 = default value.

- qcom,mdss-dsi-t-clk-pre-extend:	Boolean that specifies whether to enable t_clk_pre counter

					increment by 2 byteclk.

- qcom,mdss-dsi-stream:			Specifies the packet stream to be used.

					0 = stream 0 (default)

					1 = stream 1
@@ -660,6 +662,7 @@ Example: 
		qcom,lanes-per-sublink = <2>;

		qcom,mdss-dsi-t-clk-post = <0x20>;

		qcom,mdss-dsi-t-clk-pre = <0x2c>;

		qcom,mdss-dsi-t-clk-pre-extend;

		qcom,mdss-dsi-stream = <0>;

		qcom,mdss-dsi-mdp-trigger = <0>;

		qcom,mdss-dsi-dma-trigger = <0>;

drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c

+8 −0
Original line number Diff line number Diff line
@@ -102,6 +102,14 @@ void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl, 
	dsi_setup_trigger_controls(ctrl, cfg);

	dsi_split_link_setup(ctrl, cfg);



	/* Setup T_CLK_PRE extend register */

	reg_value = DSI_R32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_ENABLE);

	if (cfg->t_clk_pre_extend)

		reg_value |= BIT(0);

	else

		reg_value &= ~BIT(0);

	DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_VIDEO_ENABLE, reg_value);



	/* Setup clocking timing controls */

	reg_value = ((cfg->t_clk_post & 0x3F) << 8);

	reg_value |= (cfg->t_clk_pre & 0x3F);

drivers/gpu/drm/msm/dsi-staging/dsi_defs.h

+3 −0
Original line number Diff line number Diff line
@@ -472,6 +472,8 @@ struct dsi_split_link_config { 
 * @t_clk_pre:           Number of byte clock cycles that the high spped clock

 *                       shall be driven prior to data lane transitions from LP

 *                       to HS mode.

 * @t_clk_pre_extend:    Increment t_clk_pre counter by 2 byteclk if set to

 *                       true, otherwise increment by 1 byteclk.

 * @ignore_rx_eot:       Ignore Rx EOT packets if set to true.

 * @append_tx_eot:       Append EOT packets for forward transmissions if set to

 *                       true.
@@ -497,6 +499,7 @@ struct dsi_host_common_cfg { 
	bool bit_swap_blue;

	u32 t_clk_post;

	u32 t_clk_pre;

	bool t_clk_pre_extend;

	bool ignore_rx_eot;

	bool append_tx_eot;

	u32 ext_bridge_num;

drivers/gpu/drm/msm/dsi-staging/dsi_panel.c

+3 −0
Original line number Diff line number Diff line
@@ -1200,6 +1200,9 @@ static int dsi_panel_parse_misc_host_config(struct dsi_host_common_cfg *host, 
		pr_debug("[%s] t_clk_pre = %d\n", name, val);

	}



	host->t_clk_pre_extend = utils->read_bool(utils->data,

						"qcom,mdss-dsi-t-clk-pre-extend");



	host->ignore_rx_eot = utils->read_bool(utils->data,

						"qcom,mdss-dsi-rx-eot-ignore");