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Commit 3b3c0ebf authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: mdss: DP PLL changes for SDM660"

parents 6cfdeb99 03cd3c9f
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+16 −5
Original line number Diff line number Diff line
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
/* Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
@@ -101,7 +101,11 @@ static struct dp_pll_vco_clk dp_vco_clk = {
};

static struct clk_fixed_factor dp_phy_pll_link_clk = {
#ifdef CONFIG_FB_MSM_MDSS
	.div = 5,
#else
	.div = 10,
#endif
	.mult = 1,

	.hw.init = &(struct clk_init_data){
@@ -416,10 +420,17 @@ int dp_config_vco_rate_14nm(struct dp_pll_vco_clk *vco,
	MDSS_PLL_REG_W(dp_res->phy_base,
		QSERDES_TX1_OFFSET + TXn_LANE_MODE_1, pdb->lane_mode_1);

	if (pdb->orientation == ORIENTATION_CC2)
	if (pdb->orientation == ORIENTATION_CC2) {
		if (dp_res->target_id == MDSS_PLL_TARGET_SDM660)
			MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xc8);
		else
			MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xc9);
	} else {
		if (dp_res->target_id == MDSS_PLL_TARGET_SDM660)
			MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xd8);
		else
			MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xd9);
	}
	wmb(); /* make sure write happens */

	/* TX Lane configuration */
+6 −2
Original line number Diff line number Diff line
@@ -148,8 +148,11 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
		pll_res->pll_interface_type = MDSS_DSI_PLL_14NM;
		pll_res->target_id = MDSS_PLL_TARGET_SDM660;
		pll_res->revision = 2;
	}
	else
	} else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_sdm660")) {
		pll_res->pll_interface_type = MDSS_DP_PLL_14NM;
		pll_res->target_id = MDSS_PLL_TARGET_SDM660;
		pll_res->revision = 2;
	} else
		goto err;

	return rc;
@@ -434,6 +437,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
	{.compatible = "qcom,mdss_dp_pll_14nm"},
	{.compatible = "qcom,mdss_hdmi_pll_28lpm"},
	{.compatible = "qcom,mdss_dsi_pll_sdm660"},
	{.compatible = "qcom,mdss_dp_pll_sdm660"},
	{}
};

+2 −2
Original line number Diff line number Diff line
@@ -207,8 +207,8 @@ static const struct parent_map mmcc_parent_map_6[] = {

static const char * const mmcc_parent_names_6[] = {
	"xo",
	"dp_link_2x_clk_divsel_five",
	"dp_vco_divided_clk_src_mux",
	"dp_phy_pll_link_clk",
	"dp_phy_pll_vco_div_clk",
	"core_bi_pll_test_se",
};