Merge "clk: qcom: Reconfigure Fabia PLL during set_rate" (36966150) · Commits · e / devices / android_kernel_xiaomi_nabu

drivers/clk/qcom/clk-alpha-pll.c

+36 −5

Original line number	Diff line number	Diff line
		@@ -124,6 +124,7 @@
		#define FABIA_TEST_CTL_HI 0x20
		#define FABIA_OPMODE 0x2c
		#define FABIA_FRAC_VAL 0x38
		#define FABIA_PLL_CAL_L_VAL 0x3f
		#define FABIA_PLL_STANDBY 0x0
		#define FABIA_PLL_RUN 0x1
		#define FABIA_PLL_OUT_MASK 0x7
		@@ -1941,6 +1942,9 @@ int clk_fabia_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		regmap_write(regmap, pll->offset + PLL_L_VAL,
		config->l);

		regmap_write(regmap, pll->offset + FABIA_CAL_L_VAL,
		FABIA_PLL_CAL_L_VAL);

		if (config->frac)
		regmap_write(regmap, pll->offset + FABIA_FRAC_VAL,
		config->frac);
		@@ -1999,7 +2003,7 @@ static int clk_fabia_pll_enable(struct clk_hw *hw)
		{
		int ret;
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 val, opmode_val, off = pll->offset, l_val;
		u32 val, opmode_val, off = pll->offset, l_val, cal_val;

		ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
		if (ret)
		@@ -2025,8 +2029,13 @@ static int clk_fabia_pll_enable(struct clk_hw *hw)
		if (ret)
		return ret;

		/* PLL has lost it's L value, needs reconfiguration */
		if (!l_val)
		ret = regmap_read(pll->clkr.regmap, pll->offset + FABIA_CAL_L_VAL,
		&cal_val);
		if (ret)
		return ret;

		/* PLL has lost it's L or CAL value, needs reconfiguration */
		if (!l_val \|\| !cal_val)
		pll->inited = false;

		if (unlikely(!pll->inited)) {
		@@ -2036,7 +2045,8 @@ static int clk_fabia_pll_enable(struct clk_hw *hw)
		pr_err("Failed to configure %s\n", clk_hw_get_name(hw));
		return ret;
		}
		pr_warn("PLL configuration lost, reconfiguration of PLL done.\n");
		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",
		clk_hw_get_name(hw));
		}

		/* Disable PLL output */
		@@ -2196,7 +2206,7 @@ static int clk_fabia_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		unsigned long rrate;
		u32 regval, l, off = pll->offset;
		u32 regval, l, off = pll->offset, cal_val;
		u64 a;
		int ret;

		@@ -2204,6 +2214,26 @@ static int clk_fabia_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		if (ret)
		return ret;

		ret = regmap_read(pll->clkr.regmap, pll->offset + FABIA_CAL_L_VAL,
		&cal_val);
		if (ret)
		return ret;

		/* PLL has lost it's CAL value, needs reconfiguration */
		if (!cal_val)
		pll->inited = false;

		if (unlikely(!pll->inited)) {
		ret = clk_fabia_pll_configure(pll, pll->clkr.regmap,
		pll->config);
		if (ret) {
		pr_err("Failed to configure %s\n", clk_hw_get_name(hw));
		return ret;
		}
		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",
		clk_hw_get_name(hw));
		}

		rrate = alpha_pll_round_rate(pll, rate, prate, &l, &a);
		/*
		* Due to limited number of bits for fractional rate programming, the
		@@ -2228,6 +2258,7 @@ static void clk_fabia_pll_list_registers(struct seq_file f, struct clk_hw hw)
		static struct clk_register_data data[] = {
		{"PLL_MODE", 0x0},
		{"PLL_L_VAL", 0x4},
		{"PLL_CAL_L_VAL", 0x8},
		{"PLL_FRAC_VAL", 0x38},
		{"PLL_USER_CTL_LO", 0xc},
		{"PLL_USER_CTL_HI", 0x10},