Merge "Merge remote-tracking branch 'quic/dev/msm-4.14-display' into msm-4.14" (52ea8574) · Commits · e / devices / android_kernel_xiaomi_nabu

arch/arm64/boot/dts/qcom/sa6155-display.dtsi

+3 −2

Original line number	Original line	Diff line number	Diff line
	@@ -179,8 +179,9 @@
	qcom,dsi-phy = <&mdss_dsi_phy0>;		qcom,dsi-phy = <&mdss_dsi_phy0>;

	clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>,		clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>,
	<&mdss_dsi0_pll PIX0_MUX_CLK>;		<&mdss_dsi0_pll PIX0_MUX_CLK>,
	clock-names = "mux_byte_clk0", "mux_pixel_clk0";		<&clock_rpmh RPMH_CXO_CLK>;
			clock-names = "mux_byte_clk0", "mux_pixel_clk0", "xo_clk";


	qcom,dsi-display-list =		qcom,dsi-display-list =

arch/arm64/boot/dts/qcom/sa8155-adp-star-display.dtsi

+6 −4

Original line number	Original line	Diff line number	Diff line
	@@ -234,9 +234,10 @@
	clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
	<&mdss_dsi0_pll PCLK_MUX_0_CLK>,		<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
	<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,		<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
	<&mdss_dsi1_pll PCLK_MUX_1_CLK>;		<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>;
	clock-names = "mux_byte_clk0", "mux_pixel_clk0",		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
	"mux_byte_clk1", "mux_pixel_clk1";		"mux_byte_clk1", "mux_pixel_clk1", "xo_clk";

	qcom,dsi-display-list =		qcom,dsi-display-list =
	<&dsi_anx_7625_1>;		<&dsi_anx_7625_1>;
	@@ -264,9 +265,10 @@
	clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
	<&mdss_dsi0_pll PCLK_MUX_0_CLK>,		<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
	<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,		<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
	<&mdss_dsi1_pll PCLK_MUX_1_CLK>;		<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>;
	clock-names = "mux_byte_clk0", "mux_pixel_clk0",		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
	"mux_byte_clk1", "mux_pixel_clk1";		"mux_byte_clk1", "mux_pixel_clk1", "xo_clk";

	qcom,dsi-display-list =		qcom,dsi-display-list =
	<&dsi_anx_7625_2>;		<&dsi_anx_7625_2>;

arch/arm64/boot/dts/qcom/sa8195p-adp-star-display.dtsi

+6 −4

Original line number	Original line	Diff line number	Diff line
	@@ -228,9 +228,10 @@
	clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
	<&mdss_dsi0_pll PCLK_MUX_0_CLK>,		<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
	<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,		<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
	<&mdss_dsi1_pll PCLK_MUX_1_CLK>;		<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>;
	clock-names = "mux_byte_clk0", "mux_pixel_clk0",		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
	"mux_byte_clk1", "mux_pixel_clk1";		"mux_byte_clk1", "mux_pixel_clk1", "xo_clk";

	qcom,dsi-display-list =		qcom,dsi-display-list =
	<&dsi_anx_7625_1>;		<&dsi_anx_7625_1>;
	@@ -258,9 +259,10 @@
	clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
	<&mdss_dsi0_pll PCLK_MUX_0_CLK>,		<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
	<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,		<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
	<&mdss_dsi1_pll PCLK_MUX_1_CLK>;		<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>;
	clock-names = "mux_byte_clk0", "mux_pixel_clk0",		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
	"mux_byte_clk1", "mux_pixel_clk1";		"mux_byte_clk1", "mux_pixel_clk1", "xo_clk";

	qcom,dsi-display-list =		qcom,dsi-display-list =
	<&dsi_anx_7625_2>;		<&dsi_anx_7625_2>;

arch/arm64/boot/dts/qcom/sdmmagpie-sde.dtsi

+5 −5

Original line number	Original line	Diff line number	Diff line
	@@ -128,9 +128,9 @@
	qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
	0xb0 0xc8 0xe0 0xf8 0x110>;		0xb0 0xc8 0xe0 0xf8 0x110>;

	qcom,sde-max-per-pipe-bw-kbps = <4500000		qcom,sde-max-per-pipe-bw-kbps = <3500000
	4500000 4500000		3500000 3500000
	4500000 4500000>;		3500000 3500000>;

	/* offsets are relative to "mdp_phys + qcom,sde-off */		/* offsets are relative to "mdp_phys + qcom,sde-off */
	qcom,sde-sspp-clk-ctrl =		qcom,sde-sspp-clk-ctrl =
	@@ -155,8 +155,8 @@
	qcom,sde-has-dest-scaler;		qcom,sde-has-dest-scaler;
	qcom,sde-max-dest-scaler-input-linewidth = <2048>;		qcom,sde-max-dest-scaler-input-linewidth = <2048>;
	qcom,sde-max-dest-scaler-output-linewidth = <2560>;		qcom,sde-max-dest-scaler-output-linewidth = <2560>;
	qcom,sde-max-bw-low-kbps = <12800000>;		qcom,sde-max-bw-low-kbps = <7100000>;
	qcom,sde-max-bw-high-kbps = <12800000>;		qcom,sde-max-bw-high-kbps = <7100000>;
	qcom,sde-min-core-ib-kbps = <2400000>;		qcom,sde-min-core-ib-kbps = <2400000>;
	qcom,sde-min-llcc-ib-kbps = <800000>;		qcom,sde-min-llcc-ib-kbps = <800000>;
	qcom,sde-min-dram-ib-kbps = <800000>;		qcom,sde-min-dram-ib-kbps = <800000>;

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+44 −17

Original line number	Original line	Diff line number	Diff line
	@@ -2282,11 +2282,20 @@ static int dsi_display_phy_power_off(struct dsi_display *display)
	return rc;		return rc;
	}		}

	static int dsi_display_set_clk_src(struct dsi_display *display)		static int dsi_display_set_clk_src(struct dsi_display *display, bool on)
	{		{
	int rc = 0;		int rc = 0;
	int i;		int i;
	struct dsi_display_ctrl m_ctrl, ctrl;		struct dsi_display_ctrl m_ctrl, ctrl;
			struct dsi_clk_link_set *src;

			/* if XO clk is defined, select XO clk src when DSI is disabled */
			if (on)
			src = &display->clock_info.mux_clks;
			else if (display->clock_info.xo_clks.byte_clk)
			src = &display->clock_info.xo_clks;
			else
			return 0;

	/*		/*
	* In case of split DSI usecases, the clock for master controller should		* In case of split DSI usecases, the clock for master controller should
	@@ -2295,8 +2304,7 @@ static int dsi_display_set_clk_src(struct dsi_display *display)
	*/		*/
	m_ctrl = &display->ctrl[display->clk_master_idx];		m_ctrl = &display->ctrl[display->clk_master_idx];

	rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl,		rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, src);
	&display->clock_info.mux_clks);
	if (rc) {		if (rc) {
	pr_err("[%s] failed to set source clocks for master, rc=%d\n",		pr_err("[%s] failed to set source clocks for master, rc=%d\n",
	display->name, rc);		display->name, rc);
	@@ -2309,8 +2317,7 @@ static int dsi_display_set_clk_src(struct dsi_display *display)
	if (!ctrl->ctrl \|\| (ctrl == m_ctrl))		if (!ctrl->ctrl \|\| (ctrl == m_ctrl))
	continue;		continue;

	rc = dsi_ctrl_set_clock_source(ctrl->ctrl,		rc = dsi_ctrl_set_clock_source(ctrl->ctrl, src);
	&display->clock_info.mux_clks);
	if (rc) {		if (rc) {
	pr_err("[%s] failed to set source clocks, rc=%d\n",		pr_err("[%s] failed to set source clocks, rc=%d\n",
	display->name, rc);		display->name, rc);
	@@ -3000,12 +3007,17 @@ static int dsi_display_clocks_init(struct dsi_display *display)
	struct dsi_clk_link_set *src = &display->clock_info.src_clks;		struct dsi_clk_link_set *src = &display->clock_info.src_clks;
	struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;		struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
	struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;		struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
			struct dsi_clk_link_set *xo = &display->clock_info.xo_clks;
	struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps);		struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps);

	num_clk = dsi_display_get_clocks_count(display);		num_clk = dsi_display_get_clocks_count(display);

	pr_debug("clk count=%d\n", num_clk);		pr_debug("clk count=%d\n", num_clk);

			dsi_clk = devm_clk_get(&display->pdev->dev, "xo_clk");
			if (!IS_ERR_OR_NULL(dsi_clk))
			xo->byte_clk = xo->pixel_clk = dsi_clk;

	for (i = 0; i < num_clk; i++) {		for (i = 0; i < num_clk; i++) {
	dsi_display_get_clock_name(display, i, &clk_name);		dsi_display_get_clock_name(display, i, &clk_name);

	@@ -6514,7 +6526,7 @@ static int dsi_display_pre_switch(struct dsi_display *display)
	goto error_ctrl_clk_off;		goto error_ctrl_clk_off;
	}		}

	rc = dsi_display_set_clk_src(display);		rc = dsi_display_set_clk_src(display, true);
	if (rc) {		if (rc) {
	pr_err("[%s] failed to set DSI link clock source, rc=%d\n",		pr_err("[%s] failed to set DSI link clock source, rc=%d\n",
	display->name, rc);		display->name, rc);
	@@ -6906,7 +6918,7 @@ int dsi_display_prepare(struct dsi_display *display)
	}		}
	}		}

	rc = dsi_display_set_clk_src(display);		rc = dsi_display_set_clk_src(display, true);
	if (rc) {		if (rc) {
	pr_err("[%s] failed to set DSI link clock source, rc=%d\n",		pr_err("[%s] failed to set DSI link clock source, rc=%d\n",
	display->name, rc);		display->name, rc);
	@@ -7134,21 +7146,11 @@ int dsi_display_pre_kickoff(struct drm_connector *connector,
	{		{
	int rc = 0;		int rc = 0;
	int i;		int i;
	bool enable;

	/* check and setup MISR */		/* check and setup MISR */
	if (display->misr_enable)		if (display->misr_enable)
	_dsi_display_setup_misr(display);		_dsi_display_setup_misr(display);

	if (params->qsync_update) {
	enable = (params->qsync_mode > 0) ? true : false;
	rc = dsi_display_qsync(display, enable);
	if (rc)
	pr_err("%s failed to send qsync commands",
	__func__);
	SDE_EVT32(params->qsync_mode, rc);
	}

	rc = dsi_display_set_roi(display, params->rois);		rc = dsi_display_set_roi(display, params->rois);

	/* dynamic DSI clock setting */		/* dynamic DSI clock setting */
	@@ -7229,6 +7231,29 @@ int dsi_display_config_ctrl_for_cont_splash(struct dsi_display *display)
	return rc;		return rc;
	}		}

			int dsi_display_pre_commit(void *display,
			struct msm_display_conn_params *params)
			{
			bool enable = false;
			int rc = 0;

			if (!display \|\| !params) {
			pr_err("Invalid params\n");
			return -EINVAL;
			}

			if (params->qsync_update) {
			enable = (params->qsync_mode > 0) ? true : false;
			rc = dsi_display_qsync(display, enable);
			if (rc)
			pr_err("%s failed to send qsync commands\n",
			__func__);
			SDE_EVT32(params->qsync_mode, rc);
			}

			return rc;
			}

	int dsi_display_enable(struct dsi_display *display)		int dsi_display_enable(struct dsi_display *display)
	{		{
	int rc = 0;		int rc = 0;
	@@ -7501,6 +7526,8 @@ int dsi_display_unprepare(struct dsi_display *display)
	pr_err("[%s] panel post-unprepare failed, rc=%d\n",		pr_err("[%s] panel post-unprepare failed, rc=%d\n",
	display->name, rc);		display->name, rc);

			dsi_display_set_clk_src(display, false);

	mutex_unlock(&display->display_lock);		mutex_unlock(&display->display_lock);

	/* Free up DSI ERROR event callback */		/* Free up DSI ERROR event callback */