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Commit 35f135a3 authored by Archit Taneja's avatar Archit Taneja Committed by Rob Clark
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dt-bindings: display: msm/dsi: Add updates for SDM845



SDM845 uses a newer revision (v2.0+) of the 6G DSI controller. This
revision has another clock input at the block boundary called the byte
interface clock. Specify this new clock in the binding.

A 10nm DSI PHY is used along with the controller. Add a compatible
string for it and specify its base address/regulator supply needs.

Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 31767e00
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+6 −1
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ Required properties:
  * "core"
  For DSIv2, we need an additional clock:
   * "src"
  For DSI6G v2.0 onwards, we need also need the clock:
   * "byte_intf"
- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
  by a DSI PHY block. See [1] for details on clock bindings.
@@ -87,6 +89,7 @@ Required properties:
  * "qcom,dsi-phy-20nm"
  * "qcom,dsi-phy-28nm-8960"
  * "qcom,dsi-phy-14nm"
  * "qcom,dsi-phy-10nm"
- reg: Physical base address and length of the registers of PLL, PHY. Some
  revisions require the PHY regulator base address, whereas others require the
  PHY lane base address. See below for each PHY revision.
@@ -95,7 +98,7 @@ Required properties:
  * "dsi_pll"
  * "dsi_phy"
  * "dsi_phy_regulator"
  For DSI 14nm PHY:
  For DSI 14nm and 10nm PHYs:
  * "dsi_pll"
  * "dsi_phy"
  * "dsi_phy_lane"
@@ -112,6 +115,8 @@ Required properties:
- vcca-supply: phandle to vcca regulator device node
  For 14nm PHY:
- vcca-supply: phandle to vcca regulator device node
  For 10nm PHY:
- vdds-supply: phandle to vdds regulator device node

Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY