dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY

  * "qcom,dsi-phy-28nm-lp"

  * "qcom,dsi-phy-20nm"

  * "qcom,dsi-phy-28nm-8960"

- reg: Physical base address and length of the registers of PLL, PHY and PHY

  regulator

  * "qcom,dsi-phy-14nm"

- reg: Physical base address and length of the registers of PLL, PHY. Some

  revisions require the PHY regulator base address, whereas others require the

  PHY lane base address. See below for each PHY revision.

- reg-names: The names of register regions. The following regions are required:

  For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_regulator"

  For DSI 14nm PHY:

  * "dsi_pll"

  * "dsi_phy"

  * "dsi_phy_lane"

- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating

  2 clocks: A byte clock (index 0), and a pixel clock (index 1).

- power-domains: Should be <&mmcc MDSS_GDSC>.

- vddio-supply: phandle to vdd-io regulator device node

  For 20nm PHY:

- vddio-supply: phandle to vdd-io regulator device node

- vcca-supply: phandle to vcca regulator device node

  For 14nm PHY:

- vcca-supply: phandle to vcca regulator device node

Optional properties: